AN 717: Nios II Gen2 Hardware Development Tutorial

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ID 683615
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Hardware Development Tutorial
1. Hardware Development Tutorial x
1.1. Software and Hardware Requirements 1.2. 1.3. Design Example 1.4. System Development Flow 1.5. Creating the Design Example 1.6. Document Revision History
1.4. System Development Flow x
1.4.1. Analyzing System Requirements 1.4.2. Defining and Generating the System in 1.4.3. Integrating the System into the Project 1.4.4. Developing Software with the Software Build Tools for Eclipse 1.4.5. Running and Debugging Software on the Target Board 1.4.6. Varying the Development Flow
1.5. Creating the Design Example x
1.5.1. Install the Design Files 1.5.2. Analyze System Requirements 1.5.3. Start the Software and Open the Example Project 1.5.4. Create a New System 1.5.5. Define the System in 1.5.6. Integrate the System into the Project 1.5.7. Download the Hardware Design to the Target FPGA 1.5.8. Develop Software Using the SBT for Eclipse 1.5.9. Run the Program on Target Hardware
1.5.5. Define the System in x
1.5.5.1. Specify Target FPGA and Clock Settings 1.5.5.2. Add the On-Chip Memory 1.5.5.3. Add the Processor Core 1.5.5.4. Add the JTAG UART 1.5.5.5. Add the Interval Timer 1.5.5.6. Add the System ID Peripheral 1.5.5.7. Add the PIO 1.5.5.8. Specify Base Addresses and Interrupt Request Priorities 1.5.5.9. Generate the System
1.5.6. Integrate the System into the Project x
1.5.6.1. Instantiate the System Module in the Project 1.5.6.2. Add IP Variation File 1.5.6.3. Assign FPGA Device 1.5.6.4. Assign FPGA Pin Locations 1.5.6.5. Set Timing 1.5.6.6. Compile the Project and Verify Timing
1.5.8. Develop Software Using the SBT for Eclipse x
1.5.8.1. Create a New Application and BSP from Template 1.5.8.2. Compile the Project
1. Hardware Development Tutorial

1.5.6.1. Instantiate the Qsys System Module in the Quartus II Project

Qsys outputs a design entity called the system module. The tutorial design example uses the block diagram method of design entry, so you instantiate a system module symbol first_nios2_system into the .bdf.

Note: How you instantiate the system module depends on the design entry method of the overall Quartus II project. For example, if you were using Verilog HDL for design entry, you would instantiate the Verilog module first_nios2_system defined in the file first_nios2_system.v.

To instantiate the system module in the .bdf, perform the following steps:

  1. Double-click in the empty space to the right of the input and output wires.
    The Symbol dialog box appears.
  2. Under Libraries, expand Project.
  3. Click first_nios2_system.
    The Symbol dialog box displays the first_nios2_system symbol.
  4. Click OK. You return to the .bdf schematic. The first_nios2_system symbol tracks with your mouse pointer.
  5. Position the symbol so the pins on the symbol align with the wires on the schematic.
  6. Click to anchor the symbol in place.
  7. If your target board does not have LEDs that the Nios II system can drive, you must delete the LEDG[7..0] pins. To delete the pins, perform the following steps:
    1. Click the output symbol LEDG[7..0] to select it.
    2. On your keyboard, press Delete.
  8. To save the completed .bdf, click Save on the File menu.
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