AN 717: Nios II Gen2 Hardware Development Tutorial

ID 683615
Date 9/22/2014
Document Table of Contents Compile the Project and Verify Timing

To create a .sof file, you have to compile the hardware design and then it download to the board. After the compilation completes, you must analyze the timing performance of the FPGA design to verify that the design works in hardware. To compile the project, perform the following steps:

  1. On the Processing menu, click Start Compilation.
    The Tasks window and percentage and time counters in the lower-right corner display progress. The compilation process can take several minutes. When compilation completes, a dialog box displays the message "Full Compilation was successful."
  2. Click OK. The Quartus Prime software displays the Compilation Report tab.
  3. Expand the TimeQuest Timing Analyzer category in the compilation report.
  4. Click Multicorner Timing Analysis Summary.
  5. Verify that the Worst-case Slack values are positive numbers for Setup, Hold, Recovery, and Removal.
    If any of these values are negative, the design might not operate properly in hardware. To meet timing, adjust assignments to optimize fitting, or reduce the oscillator frequency driving the FPGA.