AN 717: Nios II Gen2 Hardware Development Tutorial

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ID 683615
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Hardware Development Tutorial
1. Hardware Development Tutorial x
1.1. Software and Hardware Requirements 1.2. 1.3. Design Example 1.4. System Development Flow 1.5. Creating the Design Example 1.6. Document Revision History
1.4. System Development Flow x
1.4.1. Analyzing System Requirements 1.4.2. Defining and Generating the System in 1.4.3. Integrating the System into the Project 1.4.4. Developing Software with the Software Build Tools for Eclipse 1.4.5. Running and Debugging Software on the Target Board 1.4.6. Varying the Development Flow
1.5. Creating the Design Example x
1.5.1. Install the Design Files 1.5.2. Analyze System Requirements 1.5.3. Start the Software and Open the Example Project 1.5.4. Create a New System 1.5.5. Define the System in 1.5.6. Integrate the System into the Project 1.5.7. Download the Hardware Design to the Target FPGA 1.5.8. Develop Software Using the SBT for Eclipse 1.5.9. Run the Program on Target Hardware
1.5.5. Define the System in x
1.5.5.1. Specify Target FPGA and Clock Settings 1.5.5.2. Add the On-Chip Memory 1.5.5.3. Add the Processor Core 1.5.5.4. Add the JTAG UART 1.5.5.5. Add the Interval Timer 1.5.5.6. Add the System ID Peripheral 1.5.5.7. Add the PIO 1.5.5.8. Specify Base Addresses and Interrupt Request Priorities 1.5.5.9. Generate the System
1.5.6. Integrate the System into the Project x
1.5.6.1. Instantiate the System Module in the Project 1.5.6.2. Add IP Variation File 1.5.6.3. Assign FPGA Device 1.5.6.4. Assign FPGA Pin Locations 1.5.6.5. Set Timing 1.5.6.6. Compile the Project and Verify Timing
1.5.8. Develop Software Using the SBT for Eclipse x
1.5.8.1. Create a New Application and BSP from Template 1.5.8.2. Compile the Project
1. Hardware Development Tutorial

1.5.5.3. Add the Processor Core

You add the /f core and configure it to use 2 KB of on-chip instruction cache memory, no data cache and use static branch prediction. For this tutorial, the /f core is configured to provide a balanced trade-off between performance and resource utilization. To add a /f core to the system, perform the following steps:

  1. On the IP Catalog tab, expand Processors and Peripherals, and then click Gen2 Processor.
  2. Click Add.
    The Processor parameter editor appears, displaying the Core Nios II tab.
  3. In the Main Tab under Select an Implementation, select /f.
  4. Click Finish and return to the System Contents tab.
    The core instance appears in the system contents table. Ignore the exception and reset vector error messages. You resolve these errors in future steps.
  5. In the Name column, right-click the processor and click Rename.
  6. Type cpu and press Enter.
  7. In the Connections column, connect the clk port of the clk_0 clock source to both the clk1 port of the on-chip memory and the clk port of the processor by clicking the hollow dots on the connection line. The dots become solid indicating the ports are connected.
  8. Connect the clk_reset port of the clk_0 clock source to both the reset1 port of the on-chip memory and the reset_n port of the processor.
  9. Connect the s1 port of the on-chip memory to both the data_master port and instruction_master port of the processor.
  10. Double-click the processor row of the system contents table to reopen the Processor parameter editor.
  11. Under Reset Vector in Vectors tab, select onchip_mem.s1 in the Reset vector memory list and type 0x0 in the Reset vector offset box.
  12. Under Exception Vector, select onchip_mem.s1 in the Exception vector memory list and type 0x20 in the Exception vector offset box.
  13. Click the Caches and Memory Interfaces tab.
  14. In the Instruction cache list, select 2 Kbytes.
  15. Choose None for Data Cache size and do not change other default settings.
  16. In Advanced Features tab, select Static branch prediction type.
  17. Click Finish. You return to the System Contents tab.
    Do not change any settings on the MMU and MPU Settings and JTAG Debug tabs.
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