Intel® MAX® 10 Analog to Digital Converter User Guide

ID 683596
Date 1/03/2024
Document Table of Contents

5.3. Valid ADC Sample Rate and Input Clock Combination

Each predefined ADC sampling rate supports a list of input clock frequencies. When you configure the ALTPLL IP core to clock the ADC, use an ADC input clock frequency supported by your ADC sampling rate.

The ability to specify the ADC sampling rate allows you more design flexibility. If you are not using the maximum Intel® MAX® 10 ADC sampling rate, you get a wider settling time margin.

Table 25.  Valid Combination of ADC Sampling Rate and Input Clock
Total ADC Sampling Rate (kHz) ADC Input Clock Frequency (MHz)
2 10 20 40 80
1000 Yes Yes Yes Yes Yes
500 Yes Yes Yes
250 Yes Yes
200 Yes
125 Yes
100 Yes
50 Yes
25 Yes