Intel® MAX® 10 Analog to Digital Converter User Guide

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ID 683596
Date 1/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Analog to Digital Converter Overview 2. Intel® MAX® 10 ADC Architecture and Features 3. Intel® MAX® 10 ADC Design Considerations 4. Intel® MAX® 10 ADC Implementation Guides 5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References 6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide
1. Intel® MAX® 10 Analog to Digital Converter Overview x
1.1. ADC Block Counts in Intel® MAX® 10 Devices 1.2. ADC Channel Counts in Intel® MAX® 10 Devices 1.3. Intel® MAX® 10 ADC Vertical Migration Support 1.4. Intel® MAX® 10 Single or Dual Supply Devices 1.5. Intel® MAX® 10 ADC Conversion
1.5. Intel® MAX® 10 ADC Conversion x
1.5.1. Voltage Representation Conversion
2. Intel® MAX® 10 ADC Architecture and Features x
2.1. Intel® MAX® 10 ADC Hard IP Block 2.2. Modular ADC Core and Modular Dual ADC Core IP Cores 2.3. Intel FPGA ADC HAL Driver 2.4. ADC Toolkit for Testing ADC Performance 2.5. ADC Logic Simulation Output
2.1. Intel® MAX® 10 ADC Hard IP Block x
2.1.1. ADC Block Locations 2.1.2. Single or Dual ADC Devices 2.1.3. ADC Analog Input Pins 2.1.4. ADC Prescaler 2.1.5. ADC Clock Sources 2.1.6. ADC Voltage Reference 2.1.7. ADC Temperature Sensing Diode 2.1.8. ADC Sequencer 2.1.9. ADC Timing
2.1.7. ADC Temperature Sensing Diode x
2.1.7.1. Temperature Measurement Code Conversion 2.1.7.2. Temperature Measurement Sampling Rate
2.1.8. ADC Sequencer x
2.1.8.1. Guidelines: ADC Sequencer in Modular Dual ADC Core IP Core
2.2. Modular ADC Core and Modular Dual ADC Core IP Cores x
2.2.1. Modular ADC Core IP Core Configuration Variants 2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture
2.2.1. Modular ADC Core IP Core Configuration Variants x
2.2.1.1. Configuration 1: Standard Sequencer with Avalon-MM Sample Storage 2.2.1.2. Configuration 2: Standard Sequencer with Avalon-MM Sample Storage and Threshold Violation Detection 2.2.1.3. Configuration 3: Standard Sequencer with External Sample Storage 2.2.1.4. Configuration 4: ADC Control Core Only
2.2.2. Modular ADC Core and Modular Dual ADC Core IP Cores Architecture x
2.2.2.1. ADC Control Core 2.2.2.2. Sequencer Core 2.2.2.3. Sample Storage Core 2.2.2.4. Response Merge Core 2.2.2.5. Dual ADC Synchronizer Core 2.2.2.6. Threshold Detection Core
2.5. ADC Logic Simulation Output x
2.5.1. Fixed ADC Logic Simulation Output 2.5.2. User-Specified ADC Logic Simulation Output
3. Intel® MAX® 10 ADC Design Considerations x
3.1. Guidelines: ADC Ground Plane Connection 3.2. Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND) 3.3. Guidelines: Board Design for Analog Input 3.4. Guidelines: Board Design for ADC Reference Voltage Pin
4. Intel® MAX® 10 ADC Implementation Guides x
4.1. Creating Intel® MAX® 10 ADC Design 4.2. Customizing and Generating Modular ADC Core IP Core 4.3. Parameters Settings for Generating ALTPLL IP Core 4.4. Parameters Settings for Generating Modular ADC Core or Modular Dual ADC Core IP Core 4.5. Completing ADC Design
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References x
5.1. Modular ADC Core Parameters Settings 5.2. Modular Dual ADC Core Parameters Settings 5.3. Valid ADC Sample Rate and Input Clock Combination 5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals 5.5. Modular ADC Core Register Definitions 5.6. ADC HAL Device Driver for Nios® Processor
5.1. Modular ADC Core Parameters Settings x
5.1.1. Modular ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.2. Modular Dual ADC Core Parameters Settings x
5.2.1. Modular Dual ADC Core IP Core Channel Name to Intel® MAX® 10 Device Pin Name Mapping
5.4. Modular ADC Core and Modular Dual ADC Core Interface Signals x
5.4.1. Command Interface of Modular ADC Core and Modular Dual ADC Core 5.4.2. Response Interface of Modular ADC Core and Modular Dual ADC Core 5.4.3. Threshold Interface of Modular ADC Core and Modular Dual ADC Core 5.4.4. CSR Interface of Modular ADC Core and Modular Dual ADC Core 5.4.5. IRQ Interface of Modular ADC Core and Modular Dual ADC Core 5.4.6. Peripheral Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.7. Peripheral Reset Interface of Modular ADC Core and Modular Dual ADC Core 5.4.8. ADC PLL Clock Interface of Modular ADC Core and Modular Dual ADC Core 5.4.9. ADC PLL Locked Interface of Modular ADC Core and Modular Dual ADC Core
5.5. Modular ADC Core Register Definitions x
5.5.1. Sequencer Core Registers 5.5.2. Sample Storage Core Registers
5.6. ADC HAL Device Driver for Nios® Processor x
5.6.1. Driver API
1. Intel® MAX® 10 Analog to Digital Converter Overview
2. Intel® MAX® 10 ADC Architecture and Features
3. Intel® MAX® 10 ADC Design Considerations
4. Intel® MAX® 10 ADC Implementation Guides
5. Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP References
6. Intel® MAX® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for Intel® MAX® 10 Analog to Digital Converter User Guide

3.3. Guidelines: Board Design for Analog Input

The crosstalk requirement for analog to digital signal is -100 dB up to 2 GHz. There must be no parallel routing between analog input signals and I/O traces, and between analog input signals and FPGA I/O signal traces.
  • The ADC presents a switch capacitor load to the driving circuit. Therefore, the total RC constant, including package, trace, and parasitic driver must be less than 42.4 ns. This consideration is to ensure that the input signal is fully settled during the sampling phase.
  • If you reduce the total sampling rate, you can calculate the required settling time as 0.45 ÷ FS > 10.62 × RC constant .
  • To gain more total RC margin, Intel recommends that you make the driver source impedance as low as possible:
    • For non-prescaler channel—less than 1 kΩ
    • For prescaler channel—less than 11 Ω
    Note: Not adhering to the source impedance recommendation may impact parameters such as total harmonic distortion (THD), signal-to-noise and distortion ratio (SINAD), differential non-linearity (DNL), and integral non-linearity (INL).

Trace Routing

  • If possible, route the switching I/O traces on different layers.
  • There is no specific requirement for input signal trace impedance. However, the DC resistance for the input trace must be as low as possible.
  • Route the analog input signal traces as adjacent as possible to REFGND if there is no REFGND plane.
  • Use REFGND as ground reference for the ADC input signal.
  • For prescaler-enabled input signal, set the ground reference to REFGND. Performance degrades if the ground reference of prescaler-enabled input signal is set to common ground (GND).

Input Low Pass Filter Selection

  • Intel recommends that you place a low pass filter to filter out high frequency noise being aliased back onto the input signal.
  • Place the low pass filter as close as possible to the analog input signals.
  • The cut off frequency depends on the analog input frequency. Intel recommends that the Fcutoff @ -3dB is at least two times the input frequency.
  • You can download the ADC input SPICE model for ADC front end board design simulation from the Intel website.
Table 11.  RC Constant and Filter Value

This table is an example of the method to quantify the RC constant and identify the RC filter value.

Total RC Constant = (RDRIVER + RBOARD + RPACKAGE + RFILTER) × (CDRIVER + CBOARD + CPACKAGE + CFILTER + CPIN)

Driver Board Package Pin Capacitance (pF) RC Filter Fcutoff @ -3dB (MHz) Total RC Constant (ns) Settling Time (ns)
R (Ω) C (pF) R (Ω) C (pF) R (Ω) C (pF) R (Ω) C (pF)
5 2 5 17 3 5 6 60 550 4.82 42.34 42.4
10 2 5 17 3 5 6 50 580 5.49 41.48 42.4
Figure 26. Passive Low Pass Filter Example


Figure 27. First Order Active Low Pass Filter ExampleThis figure is an example. You can design nth order active low pass filter.


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