AN 100: In-System Programmability Guidelines

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ID 683546
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. In-System Programmability Guidelines
1. In-System Programmability Guidelines x
1.1. General ISP Guideline 1.2. IEEE Std. 1149.1 Signals 1.3. Sequential versus Concurrent Programming 1.4. ISP Troubleshooting Guidelines 1.5. ISP through Embedded Processors 1.6. ISP through In-Circuit Testers 1.7. Document Revision History
1.1. General ISP Guideline x
1.1.1. Operating Conditions 1.1.2. User Flash Memory Operations During In-System Programming 1.1.3. Interrupting In-System Programming 1.1.4. MultiVolt Devices and Power-Up Sequences 1.1.5. I/O Pins Tri-Stated During In-System Programming 1.1.6. Pull-Up and Pull-Down of JTAG Pins During In-System Programming
1.1.1. Operating Conditions x
1.1.1.1. ISP Voltage 1.1.1.2. Input Voltages
1.2. IEEE Std. 1149.1 Signals x
1.2.1. TCK Signal 1.2.2. Programming Through a Download Cable 1.2.3. Disabling IEEE Std. 1149.1 Circuitry JTAG Permanently Disabled (MAX 7000S, MAX 7000B, MAX 7000A, MAX 7000AE and MAX 3000A Devices) JTAG Permanently Disabled (MAX 10, MAX V, MAX II, MAX 9000 and MAX 9000A Devices) JTAG Enabled for ISP or BST and Disabled in User Mode 1.2.4. Working with Different Voltage Levels
1.3. Sequential versus Concurrent Programming x
1.3.1. Sequential Programming 1.3.2. Concurrent Programming 1.3.3. Selecting Sequential or Concurrent Programming 1.3.4. Devices in Different Modes
1.4. ISP Troubleshooting Guidelines x
1.4.1. Invalid ID and Unrecognized Device Messages 1.4.2. Verify the JTAG Chain Continuity 1.4.3. Check the Voltage Levels of the Board During In-System Programming 1.4.4. Random Signals on JTAG Pins 1.4.5. Software Issues
1.5. ISP through Embedded Processors x
1.5.1. Processor and Memory Requirements 1.5.2. Porting the Jam Player
1. In-System Programmability Guidelines

1.2.3. Disabling IEEE Std. 1149.1 Circuitry

If your design does not use ISP or boundary-scan test (BST) circuitry, Altera recommends disabling the IEEE Std. 1149.1 circuitry

Table 2.  Disabling IEEE Std.1149.1 Circuitry in MAX Devices
Device Permanently Disabled Enabled for ISP and BST, Disabled During User Mode
Max 10
  • Pull the TMS and TDI signal high
  • Pull the TCK signal low
MAX II Either:
  • Pull the TMS signal high and the TCK signal low
or
  • Pull the TMS signal high before pulling the TCK signal high
MAX V
MAX 9000
MAX 9000A
MAX 7000S Turn off the Enable JTAG BST Support option in the Quartus II software. Either:
  • Pull the TMS signal high and the TCK signal low
or
  • Pull the TMS signal high before pulling the TCK signal high
MAX 7000B
MAX 7000A
MAX 7000AE
MAX 3000A

JTAG Permanently Disabled (MAX 7000S, MAX 7000B, MAX 7000A, MAX 7000AE and MAX 3000A Devices)

You can use MAX 7000S, MAX 7000B, MAX 7000A, MAX 7000AE, and MAX 3000A device JTAG pins as either JTAG ports or I/O pins. You must specify how the pins will be used before compiling your design in the Quartus II software by turning the Enable JTAG BST Support option on or off. When you turn on this option, the pins act as JTAG ports for in-system programming and boundary-scan testing; when you turn off this option, the pins act as I/O pins and you cannot perform in-system programming or boundary-scan testing.

JTAG Permanently Disabled (MAX 10, MAX V, MAX II, MAX 9000 and MAX 9000A Devices)

By default, the JTAG circuitry is always enabled in MAX 10, MAX V, MAX II, MAX 9000, and MAX 9000A devices after power-up. You must enable the JTAG circuitry during ISP and boundary-scan testing, but must be disabled at all times. Therefore, if you do not plan to use the ISP and BST circuitry, you can disable the circuitry through the JTAG pins. To disable JTAG, the JTAG specification instructs you to pull the TMS signal high but does not explain what to do with the TCK signal. Altera recommends pulling the TMS signal high and the TCK signal low. Pulling the TCK signal low ensures that a rising edge does not occur on the TCK signal during the power-up sequence.

You can pull the TCK signal high, but only after you pull the TMS signal high. Pulling the TMS signal high first ensures that the rising edges on the TCK signal do not cause the JTAG state machine to leave the test-logic-reset state.

JTAG Enabled for ISP or BST and Disabled in User Mode

For Altera ISP-capable devices that use JTAG for either in-system programming or boundary-scan testing, you must enable the JTAG circuitry during ISP and BST but must be disabled at all other times. You control JTAG operation through the JTAG pins. To disable the JTAG circuitry on MAX 10, MAX V, MAX II, MAX 9000, and MAX 9000A devices permanently, either pull the TMS signal high and the TCK signal low, or pull the TMS signal high before pulling the TCK signal high.

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