AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design

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ID 683534
Date 1/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design Generating the 10G USXGMII Ethernet Example Design Reference Design Walk Through Debugging the Reference Design Document Revision History for AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design x
Reference Design Features Reference Design Components
Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design x
Hardware Requirements Software Requirements
Generating the 10G USXGMII Ethernet Example Design x
Procedure Design Example Parameters
Reference Design Walk Through x
Setting Up Aquantia AQR105 Evaluation Board Setting Up Intel® Arria® 10 GX Transceiver SI Development Kit Running Basic Packet Transfer Changing Speed between 1 Gbps to 10Gbps
Changing Speed between 1 Gbps to 10Gbps x
USXGMII Ethernet PHY Configuration and Status Registers
Debugging the Reference Design x
Setting Up Loopback Mode for Intel® Arria® 10 GX Transceiver SI Development Kit Setting Aquantia AQR105 Ethernet PHY to Loopback Mode
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design
Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design
Generating the 10G USXGMII Ethernet Example Design
Reference Design Walk Through
Debugging the Reference Design
Document Revision History for AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design

Procedure

Figure 2. Example Design Tab
  1. Select Tools > IP Catalog to open the IP Catalog and select Low Latency Ethernet 10G MAC.
    The IP parameter editor appears.
  2. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK.
  3. To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design.
    The Parameter Editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab.
  4. Specify the parameters in the Example Design tab.
  5. Click the Generate Example Design button.
The software generates all design files in sub-directories. You require these files to run simulation, compilation, and hardware testing.
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