USXGMII Ethernet PHY Configuration and Status Registers
Register Name | Address | Description | Access | HW Reset Value |
---|---|---|---|---|
usxgmii_control | 0x400 |
Bit [0]: USXGMII_ENA:
|
RW |
0x0 |
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA is set to 1:
|
RW | 0x1 | ||
Bit [4:2]: USXGMII_SPEED is the operating speed of the PHY in USXGMII mode and USE_USXGMII_AN is set to 0.
|
RW | 0x0 | ||
Bit [8:5]: Reserved | — | — | ||
Bit [9]: RESTART_AUTO_NEGOTIATION Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted |
RWC (hardware self-clear) | 0x0 | ||
Bit [15:10]: Reserved | — | — | ||
Bit [30:16]: Reserved | — | — | ||
usxgmii_status | 0x401 | Bit [1:0]: Reserved |
— | — |
Bit [2]: LINK_STATUS indicates link status for USXGMII all speeds
|
RO | 0x0 | ||
Bit [3]: Reserved | — | — | ||
Bit [4]: Reserved | — | — | ||
Bit [5]: AUTO_NEGOTIATION_COMPLETE A value of 1 indicates the Auto-Negotiation process is completed. |
RO | 0x0 | ||
Bit [15:6]: Reserved | — | — | ||
Bit [31:16]: Reserved | — | — | ||
Reserved | 0x402:0x404 | — | — | — |
usxgmii_partner_ability | 0x405 | Bit [0]: Reserved | — | — |
Bit [6:1]: Reserved | — | — | ||
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient ethernet (EEE) clock stop is supported.
|
RO | 0x0 | ||
Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
|
RO | 0x0 | ||
Bit [11:9]: SPEED
|
RO | 0x0 | ||
Bit [12]: DUPLEX
Indicates the duplex mode.
|
RO | 0x0 | ||
Bit [13]: Reserved | — | — | ||
Bit [14]: ACKNOWLEDGE A value of 1 indicates that the device has received three consecutive matching ability values from its link partner. |
RO | 0x0 | ||
Bit [15]: LINK
Indicates the link status.
|
RO | 0x0 | ||
Bit [31:16]: Reserved | RO | — | ||
Reserved | 0x406:0x411 | — | — | — |
usxgmii_link_timer | 0x412 | Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP Core. The reset value sets the link timer to approximately 1.6 ms. Bits [13:0] are reserved and always set to 0. |
[19:14]: RW [13:0]: RO |
[19:14]: 0x1F [13:0]: 0x0 |
Reserved | 0x413:0x41F | — | — | — |
phy_serial_loopback | 0x461 | Bit [0]
|
RW | 0x0 |
Bit [15:1]: Reserved | — | — | ||
Bit [31:16]: Reserved | — | — |