AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design

ID 683534
Date 1/12/2018
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USXGMII Ethernet PHY Configuration and Status Registers

Table 4.  10G USXGMII Ethernet PHY Configuration and Status Registers Description
Register Name Address Description Access HW Reset Value
usxgmii_control 0x400
Bit [0]: USXGMII_ENA:
  • 0 : 10GBASE-R mode
  • 1 : USXGMII mode

RW

0x0
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA is set to 1:
  • 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the USXGMII_SPEED register.
  • 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto-Negotiation.
RW 0x1
Bit [4:2]: USXGMII_SPEED is the operating speed of the PHY in USXGMII mode and USE_USXGMII_AN is set to 0.
  • 3’b000: Reserved
  • 3’b001: Reserved
  • 3’b010: 1G
  • 3’b011: 10G
  • 3’b100: 2.5G
  • 3’b101: 5G
  • 3’b110: Reserved
  • 3’b111: Reserved
RW 0x0
Bit [8:5]: Reserved
Bit [9]: RESTART_AUTO_NEGOTIATION

Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted

RWC (hardware self-clear) 0x0
Bit [15:10]: Reserved
Bit [30:16]: Reserved
usxgmii_status 0x401

Bit [1:0]: Reserved

Bit [2]: LINK_STATUS indicates link status for USXGMII all speeds
  • 1: Link is established
  • 0: Link synchronization is lost, a 0 is latched
RO 0x0
Bit [3]: Reserved
Bit [4]: Reserved
Bit [5]: AUTO_NEGOTIATION_COMPLETE

A value of 1 indicates the Auto-Negotiation process is completed.

RO 0x0
Bit [15:6]: Reserved
Bit [31:16]: Reserved
Reserved 0x402:0x404
usxgmii_partner_ability 0x405 Bit [0]: Reserved
Bit [6:1]: Reserved
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient ethernet (EEE) clock stop is supported.
  • 0: Not supported
  • 1: Supported
RO 0x0
Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
  • 0: Not supported
  • 1: Supported
RO 0x0
Bit [11:9]: SPEED
  • 3'b000: 10M
  • 3'b001: 100M
  • 3'b010: 1G
  • 3'b011: 10G
  • 3'b100: 2.5G
  • 3'b101: 5G
  • 3'b110: Reserved
  • 3'b111: Reserved
RO 0x0
Bit [12]: DUPLEX
Indicates the duplex mode.
  • 0: Half duplex
  • 1: Full duplex
RO 0x0
Bit [13]: Reserved
Bit [14]: ACKNOWLEDGE

A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.

RO 0x0
Bit [15]: LINK
Indicates the link status.
  • 0: Link down
  • 1: Link up
RO 0x0
Bit [31:16]: Reserved RO
Reserved 0x406:0x411
usxgmii_link_timer 0x412

Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP Core.

The reset value sets the link timer to approximately 1.6 ms.

Bits [13:0] are reserved and always set to 0.

[19:14]: RW

[13:0]: RO

[19:14]: 0x1F

[13:0]: 0x0

Reserved 0x413:0x41F
phy_serial_loopback 0x461 Bit [0]
  • 0: Disables the PHY serial loopback
  • 1: Enables the PHY serial loopback
RW 0x0
Bit [15:1]: Reserved
Bit [31:16]: Reserved

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