AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design

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ID 683534
Date 1/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design Generating the 10G USXGMII Ethernet Example Design Reference Design Walk Through Debugging the Reference Design Document Revision History for AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design x
Reference Design Features Reference Design Components
Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design x
Hardware Requirements Software Requirements
Generating the 10G USXGMII Ethernet Example Design x
Procedure Design Example Parameters
Reference Design Walk Through x
Setting Up Aquantia AQR105 Evaluation Board Setting Up Intel® Arria® 10 GX Transceiver SI Development Kit Running Basic Packet Transfer Changing Speed between 1 Gbps to 10Gbps
Changing Speed between 1 Gbps to 10Gbps x
USXGMII Ethernet PHY Configuration and Status Registers
Debugging the Reference Design x
Setting Up Loopback Mode for Intel® Arria® 10 GX Transceiver SI Development Kit Setting Aquantia AQR105 Ethernet PHY to Loopback Mode
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design
Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design
Generating the 10G USXGMII Ethernet Example Design
Reference Design Walk Through
Debugging the Reference Design
Document Revision History for AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design

Running Basic Packet Transfer

Follow these steps to run basic packet transfer using the reference design once the links between Intel 1G/2.5G/5G/10G Multi-rate Ethernet PHY and Aquantia AQR105 Ethernet PHY are successfully connected:

  1. Depending on which Intel® Arria® 10 GX Transceiver SI development kit you would like the loop back mechanism to be, enable the Avalon® ST interface loop back in the System Console using the following command: 
    SET_TRAFFIC_CONTROLLER_STD_CHANNEL_BASE_ADDR 1
SET_AVALON_ST_LOOPBACK_ENA
  2. In the System Console from the Intel® Arria® 10 GX Transceiver SI development kit without the Avalon® ST interface loop back, use the following command to start packets transfer. This reference design connects channel 1 of the transceiver to the SFP+ interface.
    TEST_EXT_LB <channel> <speed> <burst_size>.
    Example: TEST_EXT_LB 1 10G 80000000.
The following diagram shows an example of successful packets transfer during basic packet transfer test.
Figure 6. Example of Basic Transfer Test Result
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