AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design

ID 683534
Date 1/12/2018
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Setting Up Loopback Mode for Intel® Arria® 10 GX Transceiver SI Development Kit

Follow these steps to setup loopback mode on Intel® Arria® 10 GX Transceiver SI Development Kit.

Figure 8. Loopback Mode Setup for Intel® Arria® 10 GX Transceiver SI Development Kit
  1. Remove the Aquantia's 28nm AQrate* ARQ105 evaluation board from the Intel® Arria® 10 GX Transceiver SI Development Kit and connect the SFP+ loopback adapter module to the SFP+ connector on both the development kits.
  2. Verify the Clock Control on both the development kit are set to the following values:
    • Y5 is set to 644.53125 MHz
    • Y6 is set to 125 MHz
  3. Set correct port ID for the System Console, if you are using the same host for both Intel® Arria® 10 GX Transceiver SI Development Kit. Refer to Setting Up Intel Arria 10 GX Transceiver SI Development Kit to setup the System Console's port ID.
    Example:
    • System Console from LL10G_10G_USXGMII/hwtesting/system_console_pod13_A is set to 0.
    • System Console from LL10G_10G_USXGMII/hwtesting/system_console_pod13_B is set to 1.
  4. Run the basic packet transmission test using the following command and observe the transmission result for error packets.
    TEST_EXT_LB <channel> <speed> <burst_size>

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