AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution with Aquantia* Ethernet PHY Reference Design

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ID 683534
Date 1/12/2018
Public
Document Table of Contents
Document Table of Contents x
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design Generating the 10G USXGMII Ethernet Example Design Reference Design Walk Through Debugging the Reference Design Document Revision History for AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design x
Reference Design Features Reference Design Components
Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design x
Hardware Requirements Software Requirements
Generating the 10G USXGMII Ethernet Example Design x
Procedure Design Example Parameters
Reference Design Walk Through x
Setting Up Aquantia AQR105 Evaluation Board Setting Up Intel® Arria® 10 GX Transceiver SI Development Kit Running Basic Packet Transfer Changing Speed between 1 Gbps to 10Gbps
Changing Speed between 1 Gbps to 10Gbps x
USXGMII Ethernet PHY Configuration and Status Registers
Debugging the Reference Design x
Setting Up Loopback Mode for Intel® Arria® 10 GX Transceiver SI Development Kit Setting Aquantia AQR105 Ethernet PHY to Loopback Mode
AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design
Getting Started Intel® Arria® 10 Multi Speed Ethernet Solution and Aquantia Ethernet PHY Reference Design
Generating the 10G USXGMII Ethernet Example Design
Reference Design Walk Through
Debugging the Reference Design
Document Revision History for AN 838: Interoperability between Intel® Arria® 10 NBASE-T Ethernet Solution and Aquantia Ethernet PHY Reference Design

Reference Design Components

The following table describe the components available in the reference design:
Table 1.  Reference Design Components
Component Description
10G USXGMII Design Example Components
Intel FPGA Low Latency Ethernet 10G MAC IP core The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration:
  • Speed: 1G/2.5G/5G/10G (USXGMII)
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • Use legacy XGMII Interface: Not selected
  • Use legacy Avalon Memory-Mapped Interface: Not selected
  • Use legacy Avalon Streaming Interface: Selected
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with USXGMII variant.
Channel address decoder Decodes the addresses of the components in each Ethernet channel.
Multi-channel address decoder Decodes the addresses of the components used by all channels, such as the Master ToD module.
Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.
Transceiver Reset Controller The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver.
ATX PLL Generates a TX serial clock for the Intel® Arria® 10 transceiver.
fPLL Generates clocks for all design components
Traffic controller The traffic controller consists of:
  • Traffic generator: generate burst packets to the MAC for transmission.
  • Traffic monitor: receive burst packets from MAC.
JTAG to Avalon Master Bridge This IP core provides a connection between the System Console and Platform Designer (Standard) through a physical interface. The System Console initiates Avalon® Memory Mapped transactions by sending encoded streams of bytes through the bridge's physical interface.
Aquantia Ethernet PHY components
Aquantia AQR105 Ethernet PHY Ethernet PHY device on the Aquantia 28nm AQrate* ARQ105 evaluation board.
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