Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/17/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.2.1. Simulation Results

Testbench writes 4 KB of incrementing pattern to on-chip memory and read back via Avalon-MM PIO interface. This design example testbench doesn’t simulate H2D/D2H data movers.

Figure 3. Simulation Log
Figure 4. Simulation Waveform