MAX® 10 Embedded Multipliers User Guide

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ID 683467
Date 3/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 Embedded Multiplier Block Overview 2. MAX® 10 Embedded Multipliers Features and Architecture 3. MAX® 10 Embedded Multipliers Implementation Guides 4. LPM_MULT (Multiplier) IP Core References for MAX® 10 5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 8. MAX® 10 Embedded Multipliers User Guide Archives 9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
2. MAX® 10 Embedded Multipliers Features and Architecture x
2.1. Embedded Multipliers Architecture 2.2. Embedded Multipliers Operational Modes
2.1. Embedded Multipliers Architecture x
2.1.1. Input Register 2.1.2. Multiplier Stage 2.1.3. Output Register
2.2. Embedded Multipliers Operational Modes x
2.2.1. 18-Bit Multipliers 2.2.2. 9-Bit Multipliers
3. MAX® 10 Embedded Multipliers Implementation Guides x
3.1. Files Generated by IP Cores
3.1. Files Generated by IP Cores x
3.1.1. Verilog HDL Prototype Location 3.1.2. VHDL Component Declaration Location
4. LPM_MULT (Multiplier) IP Core References for MAX® 10 x
4.1. LPM_MULT Parameter Settings 4.2. Signals
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 x
5.1. ALTMULT_ACCUM Parameter Settings 5.2. ALTMULT_ACCUM Ports
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 x
6.1. ALTMULT_ADD Parameter Settings 6.2. ALTMULT_ADD Ports
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 x
7.1. ALTMULT_COMPLEX Parameter Settings 7.2. Signals
1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide

6.1. ALTMULT_ADD Parameter Settings

There are three groups of options: General, Extra Modes, and Multipliers.

Table 15.  ALTMULT_ADD Parameters - General This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
What is the number of multipliers? NUMBER_OF_MULTIPLIERS — 1, 2, 3, or 4 Specifies the number of multipliers. You can specify up to four multipliers.
All multipliers have similar configurations — — On or Off Turn on this option if you want all multipliers to have similar configurations.
How wide should the A input buses be? WIDTH_A — 1–256 Specifies the width of A input buses.
How wide should the B input buses be? WIDTH_B — 1–256 Specifies the width of B input buses.
How wide should the ‘result’ output bus be? WIDTH_RESULT — 1–256 Specifies the width of ‘result’ output bus.
Create a 4th asynchronous clear input option — — On or Off Turn on this option if you want to create a 4th asynchronous clear input option.
Create an associated clock enable for each clock — — On or Off Turn on this option if you want to create an associated clock enable for each clock.
What is the representation format for A inputs? REPRESENTATION_A —
  • Signed
  • Unsigned
  • Variable
 Specifies the representation format for A inputs.
‘signa’ input controls the sign (1 signed/0 unsigned) PORT_SIGNA Input Representation > What is the representation format for A inputs? = Variable More Options High ‘signa’ input indicates signed and low ‘signa’ input indicates unsigned.
Register ‘signa’ input — Input Representation > More Options On or Off Turn on this option if you want to enable the register of ‘signa’ input
Add an extra pipeline register — Input Representation > More Options On or Off Turn on this option if you want to enable the extra pipeline register
Input Register > What is the source for clock input? SIGNED_REGISTER_A Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Input Register > What is the source for asynchronous clear input? SIGNED_ACLR_A Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Pipeline Register > What is the source for clock input? SIGNED_PIPELINE_REGISTER_A Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? SIGNED_PIPELINE_ACLR_A Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
What is the representation format for B inputs? REPRESENTATIONS_B —
  • Signed
  • Unsigned
  • Variable
 Specifies the representation format for B inputs.
‘signb’ input controls the sign (1 signed/0 unsigned) PORT_SIGNB Input Representation > What is the representation format for B inputs? = Variable More Options High ‘signb’ input indicates signed and low ‘signb’ input indicates unsigned.
Register ‘signb’ input — Input Representation > More Options On or Off Turn on this option if you want to enable the register of ‘signb’ input
Add an extra pipeline register — Input Representation > More Options On or Off Turn on this option if you want to enable the extra pipeline register
Input Register > What is the source for clock input? SIGNED_REGISTER_B Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Input Register > What is the source for asynchronous clear input? SIGNED_ACLR_B Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Pipeline Register > What is the source for clock input? SIGNED_PIPELINE_REGISTER_B Input Representation > More Options Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? SIGNED_PIPELINE_ACLR_B Input Representation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Table 16.  ALTMULT_ADD Parameters - Extra Modes This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Create a shiftout output from A input of the last multiplier — — On or Off Turn on to create a signal from A input.
Create a shiftout output from B input of the last multiplier — — On or Off Turn on to create a signal from B input.
Register output of the adder unit — — On or Off Turn on to create a register output of the adder unit.
What is the source for clock input? OUTPUT_REGISTER
  • Outputs Configuration > Register output of the adder unit = On
  • Outputs Configuration > More Options
 Clock0–Clock3 Specifies the clock signal for the output register.
What is the source for asynchronous clear input? OUTPUT_ACLR
  • Outputs Configuration > Register output of the adder unit = On
  • Outputs Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
What operation should be performed on outputs of the first pair of multipliers? MUTIPLIER1_DIRECTION General > What is the number of multipliers? = 2, 3, or 4
  • Add
  • Subtract
  • Variable
 Specifies whether the second multiplier adds or subtracts its value from the sum. Values are add and subtract. If Variable is selected the addnsub1 port is used.
‘addnsub1’ input controls the operation (1 add/0 sub) — Adder Operation > What operation should be performed on outputs of the first pair of multipliers? = Variable More Options High ‘addnsub1’ input indicates add and low ‘addnsub1’ input indicates subtract.
Register ‘addnsub1' input — — On or Off Turn on this option if you want to enable the register of ‘addnsub1’ input
Add an extra pipeline register — — On or Off Turn on this option if you want to enable the extra pipeline register
Input Register > What is the source for clock input? ADDNSUB_MULTIPLIER_REGISTER[1] Adder Operation > More Options Clock0–Clock3 Specifies the source for clock input.
Input Register > What is the source for asynchronous clear input? ADDSUB_MULTIPLIER_ACLR[1] Adder Operation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Pipeline Register > What is the source for clock input? ADDNSUB_MULTIPLIER_PIPELINE_REGISTER[1] Adder Operation > More Options Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? ADDNSUB_MULTIPLIER_PIPELINE_ACLR[1] Adder Operation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
What operation should be performed on outputs of the second pair of multipliers? MUTIPLIER3_DIRECTION General > What is the number of multipliers? = 4 — Specifies whether the fourth and all subsequent odd-numbered multipliers add or subtract their results from the total. Values are add and subtract. If Variable is selected, the addnsub3 port is used.
‘addnsub3’ input controls the sign (1 add/0 sub) - More Options — — — High ‘addnsub3’ input indicates add and low ‘addnsub3’ input indicates subtract.
Register ‘addnsub3’ input — — On or Off Turn on this option if you want to enable the register of ‘addnsub3’ input.
Add an extra pipeline register — — On or Off Turn on this option if you want to enable the extra pipeline register.
Input Register > What is the source for clock input? ADDNSUB_MULTIPLIER_REGISTER[3] Adder Operation > More Options Clock0–Clock3 Specifies the source for clock input.
Input Register > What is the source for asynchronous clear input? ADDSUB_MULTIPLIER_ACLR[3] Adder Operation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Pipeline Register > What is the source for clock input? ADDNSUB_MULTIPLIER_PIPELINE_REGISTER[3] Adder Operation > More Options Clock0–Clock3 Specifies the source for clock input.
Pipeline Register > What is the source for asynchronous clear input? ADDNSUB_MULTIPLIER_PIPELINE_ACLR[3] Adder Operation > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Which multiplier-adder implementation should be used? DEDICATED_MULTIPLIER_CIRCUITRY —
  • Use the default implementation
  • Use dedicated multiplier circuitry (Not available for all families)
  • Use logic elements
 Specifies the multiplier-adder implementation.
Table 17.  ALTMULT_ADD Parameters - Multipliers This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Register input A of the multiplier — — On or Off Turn on to enable register input A of the multiplier.
What is the source for clock input? INPUT_REGISTER_A[0..3]
  • Input Configuration > Register input A of the multiplier = On
  • • Input Configuration > More Options
 Clock0–Clock3 Specifies the source for clock input.
What is the source for asynchronous clear input? INPUT_ACLR_A[0..3]
  • Input Configuration > Register input A of the multiplier = On
  • Input Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
Register input B of the multiplier — — On or Off Turn on to enable register input B of the multiplier.
What is the source for clock input? INPUT_REGISTER_B[0..3]
  • Input Configuration > Register input B of the multiplier = On
  • Input Configuration > More Options
 Clock0–Clock3 Specifies the source for clock input.
What is the source for asynchronous clear input? INPUT_ACLR_B[0..3]
  • Input Configuration > Register input B of the multiplier = On
  • Input Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
What is the input A of the multiplier connected to? INPUT_SOURCE_A[0..3] —
  • Multiplier input
  • Shiftin input
 Specifies the input A of the multiplier is connected to either multiplier input or shiftin input.
What is the input B of the multiplier connected to? INPUT_SOURCE_B[0..3] —
  • Multiplier input
  • Shiftin input
 Specifies the input B of the multiplier is connected to either multiplier input or shiftin input.
Register output of the multiplier — — On or Off Turn on to enable the register for output of the multiplier.
What is the source for clock input? MULTIPLIER_REGISTER[]
  • Output Configuration > Register output of the multiplier = On
  • Output Configuration > More Options
 Clock0–Clock3 Specifies the source for clock input.
What is the source for asynchronous clear input? MULTIPLIER_ACLR[]
  • Output Configuration > Register output of the multiplier = On
  • Output Configuration > More Options
  • Aclr0–Aclr2
  • None
 Specifies the source for asynchronous clear input.
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