MAX 10 Embedded Multipliers User Guide

ID 683467
Date 2/21/2017
Public
Document Table of Contents

7.1. ALTMULT_COMPLEX Parameter Settings

There are two groups of options: General and Implementation Style/Pipelining.

Table 20.  ALTMULT_COMPLEX Parameters - General This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
How wide should the A input buses be? WIDTH_A 1–256 Specifies the width of A input buses.
How wide should the B input buses be? WIDTH_B 1–256 Specifies the width of B input buses.
How wide should the ‘result’ output bus be? WIDTH_RESULT 1–256 Specifies the width of ‘result’ output bus.
What is the representation format for A inputs? REPRESENTATION_A
  • Signed
  • Unsigned
Specifies the representation format for A inputs.
What is the representation format for B inputs? REPRESENTATIONS_B
  • Signed
  • Unsigned
Specifies the representation format for B inputs.
Table 21.  ALTMULT_COMPLEX Parameters - Implementation Style/Pipelining This table lists the IP core parameters applicable to MAX® 10 devices.
GUI Parameter Parameter Condition Value Description
Which implementation style should be used? IMPLEMENTATION_STYLE Automatically select a style for best trade-off for the current settings By default automatic selection for MAX® 10 device is selected. Quartus® Prime software will determine the best implementation based on the selected device family and input width.
Output latency [] clock cycles PIPELINE 0–14 Specifies the number of clock cycles for output latency.
Create an asynchronous Clear input On or off Specifies synchronous clear for the complex multiplier. Clears the function asynchronously when the aclr port is asserted high.
Create clock enable input On or off Specifies active high clock enable for the clock port of the complex multiplier.

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