MAX® 10 Embedded Multipliers User Guide

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ID 683467
Date 3/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 Embedded Multiplier Block Overview 2. MAX® 10 Embedded Multipliers Features and Architecture 3. MAX® 10 Embedded Multipliers Implementation Guides 4. LPM_MULT (Multiplier) IP Core References for MAX® 10 5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 8. MAX® 10 Embedded Multipliers User Guide Archives 9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
2. MAX® 10 Embedded Multipliers Features and Architecture x
2.1. Embedded Multipliers Architecture 2.2. Embedded Multipliers Operational Modes
2.1. Embedded Multipliers Architecture x
2.1.1. Input Register 2.1.2. Multiplier Stage 2.1.3. Output Register
2.2. Embedded Multipliers Operational Modes x
2.2.1. 18-Bit Multipliers 2.2.2. 9-Bit Multipliers
3. MAX® 10 Embedded Multipliers Implementation Guides x
3.1. Files Generated by IP Cores
3.1. Files Generated by IP Cores x
3.1.1. Verilog HDL Prototype Location 3.1.2. VHDL Component Declaration Location
4. LPM_MULT (Multiplier) IP Core References for MAX® 10 x
4.1. LPM_MULT Parameter Settings 4.2. Signals
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10 x
5.1. ALTMULT_ACCUM Parameter Settings 5.2. ALTMULT_ACCUM Ports
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10 x
6.1. ALTMULT_ADD Parameter Settings 6.2. ALTMULT_ADD Ports
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10 x
7.1. ALTMULT_COMPLEX Parameter Settings 7.2. Signals
1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide

3.1.1. Verilog HDL Prototype Location

You can view the Verilog HDL prototype for the IP cores in the following Verilog Design Files (.v):
Table 3.  Verilog HDL Prototype Location
Integer Arithmetic IP Core Directory Verilog Design File (.v)
LPM_MULT < Quartus® Prime installation directory>\eda\synthesis lpm.v
  • ALTMULT_ACCUM
  • ALTMULT_ADD
  • ALTMULT_COMPLEX
 < Quartus® Prime installation directory>\eda\synthesis altera_mf.v
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