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1. MAX® 10 Embedded Multiplier Block Overview
2. MAX® 10 Embedded Multipliers Features and Architecture
3. MAX® 10 Embedded Multipliers Implementation Guides
4. LPM_MULT (Multiplier) IP Core References for MAX® 10
5. ALTMULT_ACCUM (Multiply-Accumulate) IP Core References for MAX® 10
6. ALTMULT_ADD (Multiply-Adder) IP Core References for MAX® 10
7. ALTMULT_COMPLEX (Complex Multiplier) IP Core References for MAX® 10
8. MAX® 10 Embedded Multipliers User Guide Archives
9. Document Revision History for the MAX® 10 Embedded Multipliers User Guide
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3.1.1. Verilog HDL Prototype Location
You can view the Verilog HDL prototype for the IP cores in the following Verilog Design Files (.v):
Integer Arithmetic IP Core | Directory | Verilog Design File (.v) |
---|---|---|
LPM_MULT | < Quartus® Prime installation directory>\eda\synthesis | lpm.v |
|
< Quartus® Prime installation directory>\eda\synthesis | altera_mf.v |