MAX 10 Embedded Multipliers User Guide

ID 683467
Date 2/21/2017
Public
Document Table of Contents
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3.1.1. Verilog HDL Prototype Location

You can view the Verilog HDL prototype for the IP cores in the following Verilog Design Files (.v):
Table 3.  Verilog HDL Prototype Location
Integer Arithmetic Megafunctions Directory Verilog Design File (.v)
LPM_MULT < Quartus® Prime installation directory>\eda\synthesis lpm.v
  • ALTMULT_ACCUM
  • ALTMULT_ADD
  • ALTMULT_COMPLEX
< Quartus® Prime installation directory>\eda\synthesis altera_mf.v