Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.14.2. Example Top-Level VHDL Module

VHDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.
library ieee;
use ieee.std_logic_1164.all; 
library altera_mf;
use altera_mf.altera_mf_components.all; 

entity MF_top is
	    port (clock, sel  : in  std_logic;				
	          a, b, datab : in  std_logic_vector(31 downto 0);			
	          result      : out std_logic_vector(31 downto 0));
end entity;

architecture arch_MF_top of MF_top is
signal wire_dataa : std_logic_vector(31 downto 0);

wire_dataa <= a when (sel = '1') else b;
inst1 : altfp_mult 
	    generic map	(
	           	pipeline => 11,
	       	    width_exp => 8,
	           	width_man => 23,		
	           	exception_handling => "no")		
	    port map (
	           	dataa => wire_dataa,
	           	datab => datab,
	           	clock => clock,
	           	result => result);	
end arch_MF_top;