Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/03/2023

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6.2.4. Replace Logic Lock (Standard) Regions

Intel® Quartus® Prime Pro Edition software introduces more simplified and flexible Logic Lock constraints, compared with previous Logic Lock regions. You must replace all Logic Lock (Standard) assignments with compatible Logic Lock assignments for migration.
To convert Logic Lock (Standard) regions to Logic Lock regions:
  1. Edit the .qsf to delete or comment out all of the following Logic Lock assignments:
    set_global_assignment -name LL_ENABLED* 
    set_global_assignment -name LL_AUTO_SIZE* 
    set_global_assignment -name LL_STATE FLOATING* 
    set_global_assignment -name LL_RESERVED*
    set_global_assignment -name LL_CORE_ONLY*
    set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE*
    set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT*
    set_global_assignment -name LL_PR_REGION*
    set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE*
    set_global_assignment -name LL_WIDTH*
    set_global_assignment -name LL_HEIGHT
    set_global_assignment -name LL_ORIGIN
    set_instance_assignment -name LL_MEMBER_OF
  2. Edit the .qsf or click Tools > Chip Planner to define new Logic Lock regions. Logic Lock constraint syntax is simplified, for example:
    set_instance_assignment -name PLACE_REGION "1 1 20 20" -to fifo1
    set_instance_assignment -name RESERVE_PLACE_REGION OFF -to fifo1
    set_instance_assignment -name CORE_ONLY_PLACE_REGION OFF -to fifo1

    Compilation fails if synthesis finds other Quartus software product's Logic Lock assignments in an Intel® Quartus® Prime Pro Edition project. The following table compares other Quartus software product region constraint support with the Intel® Quartus® Prime Pro Edition software.

    Table 23.  Region Constraints Per Edition
    Constraint Type Logic Lock (Standard) Region Support

    Other Quartus Software Products

    Logic Lock Region Support

    Intel® Quartus® Prime Pro Edition

    Fixed rectangular, nonrectangular or non-contiguous regions Full support. Full support.
    Chip Planner entry Full support. Full support.
    Periphery element assignments Supported in some instances. Full support. Use “core-only” regions to exclude the periphery.
    Nested (“hierarchical”) regions Supported but separate hierarchy from the user instance tree. Supported in same hierarchy as user instance tree.
    Reserved regions Limited support for nested or nonrectangular reserved regions. Reserved regions typically cannot cross I/O columns; use non-contiguous regions instead. Full support for nested and nonrectangular regions. Reserved regions can cross I/O columns without affecting periphery logic if the regions are "core-only".
    Routing regions Limited support via “routing expansion.” No support with hierarchical regions. Full support (including future support for hierarchical regions).
    Floating or autosized regions Full support. No support.
    Region names Regions have names. Regions are identified by the instance name of the constrained logic.
    Multiple instances in the same region Full support. Support for non-reserved regions. Create one region per instance, and then specify the same definition for multiple instances to assign to the same area. Not supported for reserved regions.
    Member exclusion Full support. No support for arbitrary logic. Use a core-only region to exclude periphery elements. Use non-rectangular regions to include more RAM or DSP columns as needed.