Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/03/2023

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Document Table of Contents

4.13. Design Planning Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.04.03 23.1
  • Updated product family name to "Intel Agilex 7."
2022.12.12 22.4
  • Updated Plan for the Target Device or Board topic for board-aware features.
2022.06.20 22.2
  • Removed obsolete Simultaneous Switching Noise Analysis topic from this basic discussion.
2022.03.28 22.1
  • Added information about Power and Thermal Calculator in Plan for Device Power Consumption.
2021.10.04 21.3
  • Added support for Questa* Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
2018.09.24 18.1.0
  • Moved information about specifying the target board to "Specifying the Target Device or Board" in Managing Projects chapter.
  • Retitled "Creating Design Specifications" to "Create a Design Specification and Test Plan."
  • Retitled "Selecting Intellectual Property Cores" to "Plan for Intellectual Property Cores."
  • Retitled "Using Standard Interfaces" to "Plan for Standard Interfaces." Corrected references to Platform Designer.
  • Retitled "Device Selection" to "Plan for the Target Device." Updated this content to correct Platform Designer names.
  • Moved "Setting Pin Assignments" to Managing Projects chapter as "Generating Pin Assignments for a Target Board."
  • Retitled "Estimating Power" to "Plan for Device Power Consumption." Reorganized this topic into sections for EPE and Power Analyzer.
  • Added link to "Simulator Support, Third-Party Simulation User Guide
  • Retitled "Planning for Device Programming or Configuration" to "Plan for Device Programming"
  • Retitled "Selecting Third-Party EDA Tools" to "Plan for other EDA Tools."
  • Retitled "Planning for On-Chip Debugging Tools" to "Plan for On-Chip Debugging Tools."
  • Retitled Design Planning with the Intel Quartus Prime Software to Design Planning
2018.05.07 18.0 Initial release as separate chapter of Getting Started User Guide.
Date Version Changes
2017.11.06 17.1.0
  • Changed instances of OpenCore Plus to Intel® FPGA IP Evaluation Mode.
  • Changed instances of Qsys to Platform Designer (Standard)
2017.05.08 17.0.0
  • Removed mentions to Integrated Synthesis.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.03 16.0.0 Added information about Development Kit selection.
2015.11.02 15.1.0
  • Added references to Interface Planning chapter.
  • Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0 Remove support for Early Timing Estimate feature.
2014.06.30 14.0.0 Updated document format.
November 2013 13.1.0 Removed HardCopy device information.
November, 2012 12.1.0 Update for changes to early pin planning feature
June 2012 12.0.0 Editorial update.
November 2011 11.0.1 Template update.
May 2011 11.0.0
  • Added link to System Design with Qsys in “Creating Design Specifications” on page 1–2
  • Updated “Simultaneous Switching Noise Analysis” on page 1–8
  • Updated “Planning for On-Chip Debugging Tools” on page 1–10
  • Removed information from “Planning Design Partitions and Floorplan Location Assignments” on page 1–15
December 2010 10.1.0
  • Changed to new document template
  • Updated “System Design and Standard Interfaces” on page 1–3 to include information about the Qsys system integration tool
  • Added link to the Product Selector in “Device Selection” on page 1–3
  • Converted information into new table (Table 1–1) in “Planning for On-Chip Debugging Options” on page 1–10
  • Simplified description of incremental compilation usages in “Incremental Compilation with Design Partitions” on page 1–14
  • Added information about the Rapid Recompile option in “Flat Compilation Flow with No Design Partitions” on page 1–14
  • Removed details and linked to Intel® Quartus® Prime Help in “Fast Synthesis and Early Timing Estimation” on page 1–16
July 2010 10.0.0
  • Added new section “System Design” on page 1–3
  • Removed details about debugging tools from “Planning for On-Chip Debugging Options” on page 1–10 and referred to other handbook chapters for more information
  • Updated information on recommended design flows in “Incremental Compilation with Design Partitions” on page 1–14 and removed “Single-Project Versus Multiple-Project Incremental Flows” heading
  • Merged the “Planning Design Partitions” section with the “Creating a Design Floorplan” section. Changed heading title to “Planning Design Partitions and Floorplan Location Assignments” on page 1–15
  • Removed “Creating a Design Floorplan” section
  • Removed “Referenced Documents” section
  • Minor updates throughout chapter
November 2009 9.1.0
  • Added details to “Creating Design Specifications” on page 1–2
  • Added details to “Intellectual Property Selection” on page 1–2
  • Updated information on “Device Selection” on page 1–3
  • Added reference to “Device Migration Planning” on page 1–4
  • Removed information from “Planning for Device Programming or Configuration” on page 1–4
  • Added details to “Early Power Estimation” on page 1–5
  • Updated information on “Early Pin Planning and I/O Analysis” on page 1–6
  • Updated information on “Creating a Top-Level Design File for I/O Analysis” on page 1–8
  • Added new “Simultaneous Switching Noise Analysis” section
  • Updated information on “Synthesis Tools” on page 1–9
  • Updated information on “Simulation Tools” on page 1–9
  • Updated information on “Planning for On-Chip Debugging Options” on page 1–10
  • Added new “Managing Metastability” section
  • Changed heading title “Top-Down Versus Bottom-Up Incremental Flows” to “Single-Project Versus Multiple-Project Incremental Flows”
  • Updated information on “Creating a Design Floorplan” on page 1–18
  • Removed information from “Fast Synthesis and Early Timing Estimation” on page 1–18
March 2009 9.0.0
  • No change to content
November 2008 8.1.0
  • Changed to 8-1/2 x 11 page size. No change to content.
May 2008 8.0.0
  • Organization changes
  • Added “Creating Design Specifications” section
  • Added reference to new details in the In-System Design Debugging section of volume 3
  • Added more details to the “Design Practices and HDL Coding Styles” section
  • Added references to the new Best Practices for Incremental Compilation and Floorplan Assignments chapter
  • Added reference to the Intel® Quartus® Prime Language Templates