Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 4/03/2023

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Document Table of Contents

6.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History

This chapter has the following revision history.
Document Version Intel® Quartus® Prime Version Changes
2023.04.03 23.1
  • Added note to Upgrade Project Assignments and Constraints about new prompt to update operating temperatures in a migrated project.
2018.09.24 18.1.0 Added information about removing assignments from the qsf file that point to legacy output files.
2018.05.07 18.0.0 First release as separate chapter of Getting Started User Guide.
2017.11.06 17.1.0
  • Added Verilog HDL Macro example.
  • Updated for latest Intel® branding conventions.
2017.05.08 17.0.0
  • Removed statement about limitations for safe state machines. The Compiler supports safe state machines. State machine inference is enabled by default.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Described unsupported Intel® Quartus® Prime Standard Edition physical synthesis options.
  • Changed title from "Remove Filling Vectors" to "Remove Unsized Constant".
2016.05.03 16.0.0
  • Added topic on Safe State Machine encoding.
  • Corrected statement about Verilog Compilation Unit.
  • Corrected typo in Modify Entity Name Assignments.
  • Clarified limitations for multiple Logic Lock instances in the same region.
2015.11.02 15.1.0
  • First version of document.