Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 9/23/2022
Public
Document Table of Contents

A.3. Reviewing Factors That Affect Throughput

The High-Level Design Reports (report.html) contain reports and tools that help you to understand the behavior of loops in your component and tasks. You can also view information about your component that is collected after simulation.

The Intel® HLS Compiler Pro Edition provides the following reports and tools that you can use to investigate the throughput of your design:
  • Loop Analysis Report

    The Loop Analysis report contains information about all the loops (coalesced, unrolled, and fused loops) in your design and their unroll statuses.

  • Loops Viewer (Alpha)

    The Loop Viewer shows the behavior of implicit and explicit loops in your design as a color-coded bar graphs. You adjust the trip counts of the loops in the viewer to see how the behavior of your design might change with different trip counts for loops.

  • Verification Statistics Report

    After you simulate your design, you can review information such as the number and type of invocations, latency, initiation interval, and throughput. for each component that the testbench calls.

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