Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 9/23/2022
Public
Document Table of Contents

A.2. Reviewing Component Architecture

The High-Level Design Reports (report.html) contain tools that show different views into the structure, interfaces, datapaths, and computation flows in your component.
The Intel® HLS Compiler Pro Edition provides the following tools you can use to investigate your design:
  • System Viewer

    The System Viewer is an interactive view of your system as a hierarchy of block diagrams of how the compiler constructed your component. These diagrams can help you understand how data flows through your component. Clicking on different parts of a digram shows you information such as the sizes and types of loads and stores, stalls, and latencies. The information is presented at various levels of granularity: system, function (component and task), block, and cluster.

  • Function Memory Viewer

    The Function Memory Viewer report shows the data connections across the memory system of your component.

  • Schedule Viewer (Beta)

    The Schedule Viewer report displays a Gantt-chart-like format that shows when each instruction is active relative to the other instructions.

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