Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 9/23/2022
Public
Document Table of Contents

1. Intel® High Level Synthesis Compiler Pro Edition User Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.3
The Intel® HLS Compiler Pro Edition User Guide provides instructions on synthesizing, verifying, and simulating IP that you design for Intel® FPGA products. The Intel® High Level Synthesis (HLS) Compiler is sometimes referred to as the i++ compiler, reflecting the name of the compiler command.

Compared to traditional RTL development, the Intel® HLS Compiler offers the following advantages:

  • Fast and easy verification
  • Algorithmic development in C++
  • Automatic integration of RTL verification with a C++ testbench
  • Powerful microarchitecture optimizations

In this publication, <quartus_installdir> refers to the location where you installed Intel® Quartus® Prime Design Suite.

The default Intel® Quartus® Prime Design Suite installation location depends on your operating system:
Windows
C:\intelFPGA_pro\22.3
Linux
/home/<username>/intelFPGA_pro/22.3

About the Intel® HLS Compiler Pro Edition Documentation Library

Documentation for the Intel® HLS Compiler Pro Edition is split across a few publications. Use the following table to find the publication that contains the Intel® HLS Compiler Pro Edition information that you are looking for:
Table 1.   Intel® High Level Synthesis Compiler Pro Edition Documentation Library
Title and Description
Release Notes

Provides late-breaking information about the Intel® HLS Compiler.

Link
Getting Started Guide

Get up and running with the Intel® HLS Compiler by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel® HLS Compiler.

Link
User Guide

Provides instructions on synthesizing, verifying, and simulating intellectual property (IP) that you design for Intel FPGA products. Go through the entire development flow of your component from creating your component and testbench up to integrating your component IP into a larger system with the Intel Quartus Prime software.

Link
Best Practices Guide

Provides techniques and practices that you can apply to improve the FPGA area utilization and performance of your HLS component. Typically, you apply these best practices after you verify the functional correctness of your component.

Link
Reference Manual

Provides reference information about the features supported by the Intel HLS Compiler. Find details on Intel® HLS Compiler command options, header files, pragmas, attributes, macros, declarations, arguments, and template libraries.

Link

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