Intel Acceleration Stack Quick Start Guide: Intel FPGA Programmable Acceleration Card D5005

ID 683394
Date 7/09/2021
Document Table of Contents

1. About this Document

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 2.0.1
This document provides a brief introduction to the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) D5005. This guide provides the instructions for the following procedures:
  • Installing the Open Programmable Acceleration Engine (OPAE) on the host Intel® Xeon® Processor to manage and access the Intel® FPGA PAC.
  • Configuring and flashing the FPGA image and Board Management Controller images.
  • Running the example hello_afu in a virtualized and non-virtualized environment.
  • Handling Graceful Thermal Shutdown

The Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs is a collection of software, firmware, and tools that allows both software and RTL developers to take advantage of the power of Intel® FPGA PACs. By offloading computationally intensive tasks to the FPGA, the acceleration platform frees the Intel® Xeon® processor for other critical processing tasks.

Figure 1.  Intel® FPGA PAC Platform Hardware and Software Overview