F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 10/04/2022
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Application (APPS) 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Application (APPS) x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. SR-IOV Applications (APPS)
2.2.1.2. SR-IOV Applications (APPS) x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module 3.3.1.2. PIO Design Example Testbench 3.3.1.3. SR-IOV Design Example Testbench 3.3.1.4. Performance Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2. Design Example Description

The F-Tile Avalon-ST IP for PCI Express Design Example is a simple design to demonstrate the establishment of PCIe connectivity of F-Tile FPGA in Intel® Quartus® Prime. The design performs write and read sequences from the host processor to the target device through PCIe Intel® Quartus® Prime Hard IP. The Programmed Input/Output (PIO) application block is needed to handle the translation from PCIe TLP to AVMM protocol.

Table 2.  F-Tile Avalon-ST IP Design Examples
Design Example Hard IP Mode Simulation Hardware
PIO Gen4 x16 512-bit Endpoint

Supports VCS* , Siemens* EDA, QuestaSim* , and Xcelium* simulators.

Supports Intel® Agilex™ F-Series F-Tile ES0 FPGA Development Kit.

Gen4 x8x8 256-bit Endpoint
Gen4 x8 256-bit Endpoint
Gen3 x16 512-bit Endpoint
Gen3 x8x8 256-bit Endpoint
Gen3 x8x8 256-bit Endpoint
SR-IOV Gen4 x16 512-bit Endpoint
Gen3 x16 512-bit Endpoint
Performance Gen4 x16 512-bit Endpoint

Supports VCS* simulators.

Note:
  1. Design examples only support the default settings in the Parameter Editor of the F-Tile Avalon Streaming IP for PCI Express.

Section Content
Programmed Input/Output Design Example
Single Root I/O Virtualization (SR-IOV) Design Example
Performance Design Example

Level Two Title