F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 10/04/2022
Public

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Document Table of Contents

2. Design Example Description

The F-Tile Avalon-ST IP for PCI Express Design Example is a simple design to demonstrate the establishment of PCIe connectivity of F-Tile FPGA in Intel® Quartus® Prime. The design performs write and read sequences from the host processor to the target device through PCIe Intel® Quartus® Prime Hard IP. The Programmed Input/Output (PIO) application block is needed to handle the translation from PCIe TLP to AVMM protocol.

Table 2.  F-Tile Avalon-ST IP Design Examples
Design Example Hard IP Mode Simulation Hardware
PIO Gen4 x16 512-bit Endpoint

Supports VCS* , Siemens* EDA, QuestaSim* , and Xcelium* simulators.

Supports Intel® Agilex™ F-Series F-Tile ES0 FPGA Development Kit.

Gen4 x8x8 256-bit Endpoint
Gen4 x8 256-bit Endpoint
Gen3 x16 512-bit Endpoint
Gen3 x8x8 256-bit Endpoint
Gen3 x8x8 256-bit Endpoint
SR-IOV Gen4 x16 512-bit Endpoint
Gen3 x16 512-bit Endpoint
Performance Gen4 x16 512-bit Endpoint

Supports VCS* simulators.

Note:
  1. Design examples only support the default settings in the Parameter Editor of the F-Tile Avalon Streaming IP for PCI Express.