F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 10/04/2022
Public

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Document Table of Contents

2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)

The DUT component is the F-Tile Avalon-ST IP for PCI Express Hard IP configured as Endpoint interacting with the root complex/switch on one end, and drives the received TLP data to the SR-IOV application at the other end. The DUT component translates the PCIe serial link transfer interface to Avalon-ST interface.