F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 10/04/2022
Public

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2.1.1.2.4. Completion Module

When both Completion command from Read Write Module and read data from Avalon-MM interface are available, Completion State Machine captures the information. The Completion command will be stored into the Completion command FIFO. The read data will be stored into Aligned Completion Data Buffer after shifted by the Barrel Shifter. The stored Completion command and read data will be shifted out to the PCIe upstream through TX Completion.