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Ixiasoft
1. About the Unified FFT Intel FPGA IPs
2. Getting Started with the Unified FFT Intel FPGA IP
3. Bit-reverse Intel® FPGA IP
4. FFT Intel FPGA IP
5. Parallel FFT Intel FPGA IP
6. Variable Size Bit-reverse Intel FPGA IP
7. Variable Size FFT Intel FPGA IP
8. Unified FFT Intel FPGA IPs User Guide Archive
9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide
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Ixiasoft
1. About the Unified FFT Intel FPGA IPs
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 21.1 |
| IP Version 1.0.0 |
The Unified FFT IPs comprise the Bit-reverse Intel FPGA IP, the FFT Intel FPGA IP, the Parallel FFT Intel FPGA IP, the Variable Size Bit-reverse Intel FPGA IP, and the Variable Size FFT Intel FPGA IP.
These IP use the same high-level synthesis technology as DSP Builder for Intel FPGAs. The high-level synthesis technology allows you to generate an IP that specifically targets the selected device family, speed grade, and frequency.
Intel recommends you use these Unified FFT IPs and not the FFT IP Core unless:
- The global enable-based flow control in Unified FFT IPs is not suitable for your requirements.
- You require 128K or 256K FFTs.
- You require bidirectional FFTs.
- You require an in-place or memory-based architecture for low-rate applications.