Unified FFT Intel FPGA IPs User Guide

ID 683366
Date 4/05/2021

1.6. Global Enable

You may specify an optional global enable signal for all Unified FFT IPs.

When a global enable signal is present, you enable the IPs when the signal is high and disable them when the signal is low. When you disable an IP, the externally visible state of the IP freezes in its last state when it was enabled. The IP ignores all inputs when it is disabled. When the IP is re-enabled it continues as if nothing happened while it was disabled.

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