3. Bit-reverse Intel® FPGA IP
This IP performs radix-2 FFT bit reverse operation. You may use this IP to bit-reverse the input or the output of FFT Intel FPGA IP.
Figure 3. Example use of the Bit-reverse Intel FPGA IP
If the input data width is smaller than the output data width, bit-reversing the input reduces memory usage in the Bit-reverse Intel FPGA IP. However, when the input is bit-reversed, the memory usage of the FFT Intel FPGA IP increases. You should experimentally determine the best configuration for memory usage.
| Name | Required | Description |
|---|---|---|
| clk | Yes | All input signals must be synchronous to this clock. |
| rst | Yes | Reset signal. The reset signal is asynchronous for Intel® Arria® 10 and Intel® Cyclone® 10 GX device; synchronous for Intel® Agilex™ and Intel® Stratix® 10. If the reset is asynchronous, deassert the reset signal synchronously to the input clock to avoid metastability issues. Select the reset polarity with the Reset polarity parameter. |
| validIn | Yes | Data valid signal. Assert this signal when input data is valid. This signal must not deassert during an FFT. Keep it asserted from the first input to last input of an FFT. |
| channelIn | Yes | Not used. Connect it to ground. |
| d | Yes | Data input signal. This signal contains the optional enable and complex or real input. The signal order is from least significant bit (LSB) to most significant bit (MSB):
|
| Name | Required | Description |
|---|---|---|
| validOut | Yes | Data valid signal. The IP asserts this signal for valid output data. |
| channelOut | Yes | Not used. |
| q | Yes | Data output signal. The signals are in the following order from least significant bit (LSB) to most significant bit (MSB):
|
| Parameter | Value | Description |
|---|---|---|
| Core Parameters | ||
| Complex input | - | Select if input should be treated as a complex value. |
| Log2(Size) | 2 to 16 | Specify the size of the FFT. For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT. |
| Reset polarity | Active High Active Low |
Select the reset polarity. |
| Signal Widths | ||
| Input width | 4 to 64 | Specify the width of the input in bits. If the input is complex, the IP applies the input width separately to the real and imaginary components of the complex signal. The total width of the complex signal is double the value of this parameter. |
| Generation Parameters | ||
| Generate a global enable signal | - | Select to generate a global enable signal, which you can use to enable and disable the IP. This enable doesn't force the output valid signal to go low. |
| Generate a software model | - | Select to generate a software model of the IP in C++ language. |
| Generate a cycle-accurate software model | - | Select to generate a cycle-accurate software model. If this option is not selected the generated software model is not cycle accurate with respect to RTL of the IP. Only available when you select Generate a software model . |
| Generate HLD external function wrappers | - | Select to generate wrapper files so that you can use the IP as an external function with HLD tools such as HLS and OpenCL. Only available if generating a software model. |
| Frequency target | 20 to 2000 | Specify the frequency at which the IP is required to operate in MHz. The Frequency target affects the RTL generation for that IP. |
| Device family | - | Specifies the device family the IP is targeting. Usually, the Intel Quartus project sets this value. If using other tools such as qsys-generate, refer to those tools’ documentation. The Device family affects the RTL generation for that IP. |
| Speed grade | - | Specifies the speed grade of the device the IP is required to operate on. Usually, the Intel Quartus project sets this value. If using other tools such as qsys-generate, refer to those tools’ documentation. The Speed grade affects the RTL generation for that IP. |