7. Variable Size FFT Intel FPGA IP
Name  Description 

clk  All input signals must be synchronous to this clock. 
rst  Reset signals. The reset signal is asynchronous for Intel® Arria® 10 and Intel® Cyclone® 10 GX device; synchronous for Intel® Agilex™ and Intel® Stratix® 10. If the reset is asynchronous, deassert the reset signal synchronously to the input clock to avoid metastability issues. Select the reset polarity with the Reset polarity parameter. 
validIn  Data valid signal. Assert this signal when input data is valid. This signal must not deassert during an FFT. Keep it asserted from the first input to last input of an FFT. 
channelIn  Not used. Connect it to ground. 
d  Data input signal. This signal contains the complex data, size of the FFT, and the optional enable. The size of the FFT is represented as a logarithm to base 2. For example, a value of 2 represents a 4point FFT and 16 represents a 64Kpoint FFT. The signal order is from least significant bit (LSB) to most significant bit (MSB):

Name  Description 

validOut  Data valid signal. The IP asserts this signal for valid output data. 
channelOut  Not used. 
q  Data output signal. This signal contains complex data and size of the FFT. The size of the FFT is represented as a logarithm to base 2. For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT. The signals are in the following order from LSB to MSB:

Parameter  Value  Description 

Core Parameters  
Inverse FFT    Specify if the operation is an FFT or inverse FFT. Turn on for an inverse FFT; turn off to compute a normal FFT. 
Bitreversed input  Specify if the input is in natural or bitreversed order. Turn on for the IP to receive its input in bitreversed order and to produce its output in natural order. Turn off for the IP to receive its input in natural order and to produce its output in bitreversed order. You can use the Variable Size Bitreverse Intel FPGA IP to bitreverse the input or the output. 

Log2(Minimum Size)  0 to 16  Specify minimum the size of the FFT. For example, a value of 0 represents a 1 point FFT and 16 represents a 64K point FFT. 
Log2(Maximum Size)  2 to 16  Specify the maximum size of the FFT. For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT. 
Datatypes  Fixed Point Floating Point 
Select a fixedpoint or floatingpoint FFT. 
Floating point types  Single Double Custom 
Select a floatingpoint format. Only available when Datatypes is Floating Point. 
Reset polarity  Active High Active Low 
Select the reset polarity. 
Signal Widths  
Input width  4 to 32  Specify the width of the complex data input in bits. The input is a complex value. The IP applies the Input width separately to the real and imaginary components of the complex signal. The total width of the complex signal is double the value of this parameter. Only available when Datatypes is Fixed Point. 
Twiddle width  4 to 32  Specify the width of the twiddle constants. The twiddle constants are complex values. The IP applies the Twiddle width separately to the real and imaginary components of the complex signal. The total width of the complex signal is double the value of this parameter. 
Exponent width  5 to 11  Specify the width of the floating point exponent. Only available when Floating point type is Custom. 
Mantissa width  7 to 52  Specify the width of the floatingpoint mantissa. Only available when Floating point type is Custom. 
Twiddle Parameters  
Pruning scheme  Full Wordgrowth Mild Pruning Prune To Width 
Select the pruning scheme. Each pruning scheme has a different effect on the datapath:
Whenever pruning is applied to the datapath only the least significant bit(s) of the datapath are removed. The IP determines the resultant scaling of the output by the maximum size of the FFT and not the current dynamic size. All FFT sizes within the range you specify pass through the same (maximum) number of pruning stages. Only available when Datatypes is Fixed Point. 
Pruning width  4 to 32  Specify the pruning width. The IP applies the Pruning width separately to the real and imaginary components of the complex signal. Only available when Pruning scheme is set to Prune To Width. 
Generation Parameters  
Generate a global enable signal    Select to generate a global enable signal, which you can use to enable and disable the IP. This enable doesn't force the output valid signal to go low. 
Generate a software model    Select to generate a software model of the IP in C++ language. 
Generate a cycleaccurate software model    Select to generate a cycleaccurate software model. If this option is not selected the generated software model is not cycle accurate with respect to RTL of the IP. Only available when you select Generate a software model . 
Generate HLD external function wrappers    Select to generate wrapper files so that you can use the IP as an external function with HLD tools such as HLS and OpenCL. Only available if generating a software model. 
Frequency target  20 to 2000  Specify the frequency at which the IP is required to operate in MHz. The Frequency target affects the RTL generation for that IP. 
Device family    Specifies the device family the IP is targeting. Usually, the Intel Quartus project sets this value. If using other tools such as qsysgenerate, refer to those tools’ documentation. The Device family affects the RTL generation for that IP. 
Speed grade    Specifies the speed grade of the device the IP is required to operate on. Usually, the Intel Quartus project sets this value. If using other tools such as qsysgenerate, refer to those tools’ documentation. The Speed grade affects the RTL generation for that IP. 