The Altera PLL IP core can generate up to 18 clock output signals for the Stratix® V and Arria® V devices, and nine clock output signals for the Cyclone® V devices. The generated clock output signals clock the core or the external blocks outside the core.
You can use the reset signal to reset the output clock value to 0 and disable the PLL output clocks.
Each output clock has a set of requested settings where you can specify the value of output frequency, phase shift, and duty cycle. The requested settings are the settings that you want to implement in your design.
The actual frequency is the closest frequency setting (best approximate of the requested settings) that can be implemented in the PLL circuit.
The output frequencies are not exact when the PLL is in fractional mode. You must be cautious with appliances that require frequencies to be exact to within less than 0.5 Hz.
For applications that require more precise clock output frequencies, turn on Enable physical output clock parameters in the parameter editor.
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