Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

ID 683359
Date 6/16/2017

Functional Description

A PLL is a frequency-control system that generates an output clock by synchronizing itself to an input clock. The PLL compares the phase difference between the input signal and the output signal of a voltage-controlled oscillator (VCO). The PLL performs phase synchronization to maintain a constant phase angle (lock) on the frequency of the input or reference signal. The synchronization or negative feedback loop of the system forces the PLL to be phase-locked.

You can configure PLLs as frequency multipliers, dividers, demodulators, tracking generators, or clock recovery circuits. You can use PLLs to generate stable frequencies, recover signals from a noisy communication channel, or distribute clock signals throughout your design.