Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

PLL Output Counter Cascading

The Altera 28 nm devices instantiate the Altera PLL IP core to allow output counter cascading. PLL cascading enables PLL to synthesize a lower frequency output which is not achievable with a single counter output.

This feature is only accessible when Enable physical output clock parameters is turned on. Turn on Make this a cascade counter to select an outclk port as the upstream counter. The upstream counter serves as the reference clock to the downstream counter and not available as a PLL output.

Only the upstream counter in the PLL output counter cascade chain supports phase shifting and only the downstream counter in the cascade chain support programmable duty cycle.

Figure 3. PLL Output Counter Cascading Mode
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