Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
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Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

PLL-to-PLL Cascading

The Altera 28 nm devices instantiate the Altera PLL IP core to allow cascading for PLLs in normal or direct mode through the Global Clock (GCLK) network.

If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting, while the destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the cascaded PLLs may amplify phase noise at certain frequencies.

The Altera PLL IP core allows you to choose the following input clock sources to cascade with an upstream PLL:

  • adjpllin—for inter-cascading between fracturable fractional PLLs.
  • cclk—for intra-cascading within fracturable fractional PLLs.

The cclk input clock source is not supported in Cyclone® V devices.

Table 7.   adjpllin Cascading for Supported Devices
Device adjpllin Cascading (Upstream PLL — Downstream PLL)
  • Arria® V GX B5 and B7
  • Arria® V GT D7
  • FRACTIONALPLL_X0_Y96 — FRACTIONALPLL_X0_Y63
  • FRACTIONALPLL_X183_Y96 — FRACTIONALPLL_X183_Y63
Arria® V GZ E5 and E7
  • FRACTIONAL_X0_Y31 — FRACTIONALPLL_X0_Y46
  • FRACTIONALPLL_X202_Y31 — FRACTIONALPLL_X202_Y46
  • Arria® V SX B3 and B5
  • Arria® V ST D3 and D5
FRACTIONALPLL_X0_Y96 — FRACTIONALPLL_X0_Y63
  • Cyclone® V E A5
  • Cyclone® V GX C4 and C5
  • Cyclone® V GT D5
  • Cyclone® V SE A2 and A4
  • Cyclone® V SX C2 and C4
FRACTIONALPLL_X0_Y14 — FRACTIONALPLL_X0_Y30
  • Cyclone® V E A7
  • Cyclone® V GX C7
  • Cyclone® V GT D7
  • Cyclone® V SE A5 and A6
  • Cyclone® V SX C5 and C6
FRACTIONALPLL_X0_Y15 — FRACTIONALPLL_X0_Y32
  • Cyclone® V E A9
  • Cyclone® V GX C9
  • Cyclone® V GT C9
  • FRACTIONALPLL_X0_Y22 — FRACTIONALPLL_X0_Y39
  • FRACTIONALPLL_X0_Y64 — FRACTIONALPLL_X0_Y81
  • Stratix® V GS D5
  • Stratix® V GX A3 (with 36 transceivers) and A4
  • FRACTIONALPLL_X0_Y31 — FRACTIONALPLL_X0_Y46
  • FRACTIONALPLL_X202_Y31 — FRACTIONALPLL_X202_Y46
Stratix® V GX B5 and B6
  • FRACTIONALPLL_X0_Y14 — FRACTIONALPLL_X0_Y30
  • FRACTIONALPLL_X0_Y76 — FRACTIONALPLL_X0_Y63
  • FRACTIONALPLL_X0_Y100 — FRACTIONALPLL_X0_Y85
  • FRACTIONALPLL_X197_Y14 — FRACTIONALPLL_X197_Y30
  • FRACTIONALPLL_X197_Y76 — FRACTIONALPLL_X197_Y63
  • FRACTIONALPLL_X197_Y100 — FRACTIONALPLL_X197_Y85
  • Stratix® V GT C5 and C7
  • Stratix® V GX A5 and A7
  • FRACTIONALPLL_X0_Y29 — FRACTIONALPLL_X0_Y44
  • FRACTIONALPLL_X0_Y91 — FRACTIONALPLL_X0_Y75
  • FRACTIONALPLL_X210_Y29 — FRACTIONALPLL_X210_Y44
  • FRACTIONALPLL_X210_Y91 — FRACTIONALPLL_X210_Y75
Stratix® V GS D6 and D8 Devices
  • FRACTIONALPLL_X0_Y41 — FRACTIONALPLL_X0_56
  • FRACTIONALPLL_X0_Y103 — FRACTIONALPLL_X0_Y87
  • FRACTIONALPLL_X208_Y41 — FRACTIONALPLL_X208_56
  • FRACTIONALPLL_X208_Y103 — FRACTIONALPLL_X208_Y87
  • Stratix® V E E9 and EB
  • Stratix® V GX A9, AB, B9, and BB
  • FRACTIONALPLL_X0_Y38 — FRACTIONALPLL_X0_Y52
  • FRACTIONALPLL_X0_Y99 — FRACTIONALPLL_X0_Y86
  • FRACTIOANLPLL_X0_Y124 — FRACTIONALPLL_X0_Y108 6
  • FRACTIONALPLL_X225_Y38 — FRACTIONALPLL_X225_Y52
  • FRACTIONALPLL_X225_Y99 — FRACTIONALPLL_X225_Y86
  • FRACTIOANLPLL_X225_Y124 — FRACTIONALPLL_X225_Y108 6
Figure 2. PLL cclk Cascading and adjpllin Cascading Modes

The clock input to PLL comes from the clock input multiplexers. The clock input multiplexers provide multiple clock sources as reference clock inputs for fractional PLL.

Table 8.  Reference Clock Inputs for Fractional PLL
Sources Description
coreclkin Core reference clock from clock network.
adjpllin Adjacent fractional PLL clock source.
refclkin[0] Clock source from adjacent PMA triplet LVPECL buffer.
refclkin[1] Clock source from adjacent PMA triplet LVPECL buffer.
clkin[0] Dedicated clock input for fractional PLL from regular I/O.
clkin[1] Dedicated clock input for fractional PLL from regular I/O.
clkin[2] Dedicated clock input for fractional PLL from regular I/O.
clkin[3] Dedicated clock input for fractional PLL from regular I/O.
rxiqclk Clock source from adjacent PMA triplet rxiqclknet. For refclk and PMA/LC cascading with fractional PLL.
refiqclk Clock source from adjacent PMA triplet rxiqclknet as refclk.
iqtxrxclk Clock source from adjacent PMA triplet iqtxrxclk as refclk.
cclk 7 C-Counter clock source.
6 This PLL is not available for Stratix® V E E9 and EB devices, and Stratix® V GX A9 and AB devices.
7 Not supported in Cyclone® V devices.
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