Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
|Intel® Quartus® Prime Design Suite 17.0|
The Altera PLL megafunction IP core allows you to configure the settings of PLL.
Altera PLL IP core supports the following features:
- Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
- Generates up to 18 clock output signals for the Arria® V and Stratix® V devices and nine clock output signals for the Cyclone® V device.
- Switches between two reference input clocks.
- Supports both the adjacent PLL (adjpllin) and the C-Counter clock source (cclk) inputs to connect with an upstream PLL in PLL cascading mode.
- Supports PLL output cascading.
- Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
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