Chip ID Intel FPGA IP Cores User Guide

ID 683336
Date 9/26/2022

Resetting the Chip ID Intel® FPGA IP Core

To reset the IP core, you must assert the reset signal for at least ten clock cycles. After you deassert the reset signal, the IP core rereads the unique chip ID from the fuse ID block. The IP core asserts the data_valid signal after completing the operation.

Note: For Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® MAX® 10, Stratix® V, Arria® V, and Cyclone® V devices, do not reset the IP core until at least tCD2UM after full chip initialization. Refer the respective device datasheet for tCD2UM value.

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