Chip ID Intel FPGA IP Cores User Guide

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ID 683336
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® FPGA IP Cores User Guide x
Device Support Chip ID Intel® Stratix® 10 FPGA IP Core Chip ID Intel® FPGA IP Cores Chip ID Intel® FPGA IP Cores User Guide Archives Document Revision History for the Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® Stratix® 10 FPGA IP Core x
Functional Description Ports Accessing Chip ID Intel® Stratix® 10 FPGA IP through Signal Tap Resetting the Chip ID Intel® Stratix® 10 FPGA IP Core
Chip ID Intel® FPGA IP Cores x
Functional Description Ports Accessing Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP through Signal Tap Resetting the Chip ID Intel® FPGA IP Core
Chip ID Intel® FPGA IP Cores User Guide

Accessing Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP through Signal Tap

Note: The Intel® Arria® 10 and Intel® Cyclone® 10 GX chip ID is inaccessible if you have other systems or IP cores accessing the JTAG simultaneously. For example, the Signal Tap II Logic Analyzer, Transceiver Toolkit, in-system signals or probes, and the SmartVID Controller IP core.

When you toggle the reset signal, the Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP cores start reading the chip ID from the Intel® Arria® 10 or Intel® Cyclone® 10 GX device. When the chip ID is ready, the Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP cores assert the data_valid signal and ends the JTAG access.

Note: Allow a delay equivalent to tCD2UM after full chip configuration before attempting to read the unique chip ID. Refer the respective device datasheet for tCD2UM value.
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