The data_valid signal starts low in the initial state where no data is being read from the device. After feeding a clock signal to the clkin input port, the Chip ID Intel® FPGA IP core reads the unique chip ID. After reading, the IP core asserts the data_valid signal to indicate that the unique chip ID value at the output port is ready for retrieval. The operation repeats only when you reset the IP core.
The chip_id[63:0] output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.