Chip ID Intel FPGA IP Cores User Guide

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ID 683336
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® FPGA IP Cores User Guide x
Device Support Chip ID Intel® Stratix® 10 FPGA IP Core Chip ID Intel® FPGA IP Cores Chip ID Intel® FPGA IP Cores User Guide Archives Document Revision History for the Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® Stratix® 10 FPGA IP Core x
Functional Description Ports Accessing Chip ID Intel® Stratix® 10 FPGA IP through Signal Tap Resetting the Chip ID Intel® Stratix® 10 FPGA IP Core
Chip ID Intel® FPGA IP Cores x
Functional Description Ports Accessing Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP through Signal Tap Resetting the Chip ID Intel® FPGA IP Core
Chip ID Intel® FPGA IP Cores User Guide

Document Revision History for the Chip ID Intel® FPGA IP Cores User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.09.26 20.3
  • Removed Project Management Best Practices link.
  • Updated Functional Description in Chip ID Intel Stratix 10 FPGA IP Core.
  • Updated Functional Description in Chip ID Intel FPGA IP Cores.
2020.10.05 20.3
  • Updated the description of the clkin and resetports in Table: Chip ID Intel® FPGA IP Core Ports Description to include Intel® MAX® 10 details.
  • Updated the Resetting the Chip ID Intel® FPGA IP Core section to include support for the Intel® MAX® 10 device.
2019.05.17 19.1 Updated the Resetting the Chip ID Intel® Stratix® 10 FPGA IP Core topic to add a second note regarding IP core instantiation guidelines.
2019.02.19 18.1 Added support for the Intel® MAX® 10 devices in the IP Cores and the Supported Devices table.
2018.12.24 18.1
  • Added the Chip ID Intel® FPGA IP Cores User Guide Archives section.
  • Restructured the document to provide more details on the respective supported devices.
2018.06.08 18.0
  • Updated the readid port description.
  • Updated the reset port description.
2018.05.07 18.0 Added readid port for Chip ID Intel® Stratix® 10 FPGA IP IP core.
Date Version Changes
December 2017 2017.12.11
  • Updated document title from Altera Unique Chip ID IP Core User Guide.
  • Added Device Support section.
  • Combined and added information from Altera Arria 10 Unique Chip ID IP Core User Guide and Stratix 10 Unique Chip ID IP Core User Guide.
  • Rebranded to Intel® .
  • Updated Functional Description.
  • Added Intel® Cyclone® 10 GX device support.
May 2016 2016.05.02
  • Removed standard IP core information and added link to Quartus Prime Handbook.
  • Updated note about Arria 10 device support.
September, 2014 2014.09.02
  • Updated document title to reflect new name of "Altera Unique Chip ID" IP core.
August, 2014 2014.08.18
  • Updated parameterization steps for legacy parameter editor.
  • Added note that this IP core does not support Arria 10 designs.
June, 2014 2014.06.30
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
September, 2013 2013.09.20 Updated to reword "Acquiring the chip ID of an FPGA device" to "Acquiring the unique chip ID of an FPGA device"

May, 2013

1.0

Initial release.

Level Two Title