Chip ID Intel FPGA IP Cores User Guide

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ID 683336
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® FPGA IP Cores User Guide x
Device Support Chip ID Intel® Stratix® 10 FPGA IP Core Chip ID Intel® FPGA IP Cores Chip ID Intel® FPGA IP Cores User Guide Archives Document Revision History for the Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® Stratix® 10 FPGA IP Core x
Functional Description Ports Accessing Chip ID Intel® Stratix® 10 FPGA IP through Signal Tap Resetting the Chip ID Intel® Stratix® 10 FPGA IP Core
Chip ID Intel® FPGA IP Cores x
Functional Description Ports Accessing Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP through Signal Tap Resetting the Chip ID Intel® FPGA IP Core
Chip ID Intel® FPGA IP Cores User Guide

Ports

Figure 1.  Chip ID Intel® Stratix® 10 FPGA IP Core Ports
Table 2.   Chip ID Intel® Stratix® 10 FPGA IP Core Ports Description
Port I/O Size (Bit) Description
clkin

Input

1

Feeds clock signal to the chip ID block. The maximum supported frequency is equivalent to your system clock.

reset

Input

1

Synchronous reset that resets the IP core.

To reset the IP core, assert the reset signal high for at least 10 clkin cycles.

data_valid

Output

1

Indicates that the unique chip ID is ready for retrieval. If the signal is low, the IP core is in initial state or in progress to load data from a fuse ID. After the IP core asserts the signal, the data is ready for retrieval at the chip_id[63..0] output port.

chip_id

Output

64

Indicates the unique chip ID according to its respective fuse ID location. The data is only valid after the IP core asserts the data_valid signal.

The value at power-up resets to 0.

The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.

readid

Input

1

The readid signal is used to read the ID value from the device. Every time the signal change value from 1 to 0, the IP core triggers the read ID operation.

You must drive the signal to 0 when unused. To start the read ID operation, drive the signal high for at least 3 clock cycles, then pull it low. The IP core starts reading the value of the chip ID.

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