1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Intel® FPGA IP Evaluation Mode
3.3. Specifying IP Core Parameters and Options
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters
3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs
3.6. IP Generation Output ( Quartus® Prime Pro Edition)
3.7. IP Core Generation Output ( Quartus® Prime Standard Edition)
3.8. Simulating
5.1. IP Architecture
5.2. Transmission Overheads and Lane Rate Calculations
5.3. Reset
5.4. Link-Up Sequence
5.5. Error Detection, Reporting, and Recovering Mechanism
5.6. CRC-32 Error Injection
5.7. FIFO ECC Protection
5.8. User Data Interface Waveforms
5.9. Signals
5.10. Accessing Configuration and Status Registers
5.1.1. Serial Lite III Streaming Source Core
5.1.2. Serial Lite III Streaming Sink Core
5.1.3. Serial Lite III Streaming IP Core Duplex Core
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
For Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices, this block is an instance of the Native PHY IP core configured for duplex Interlaken operation. The PMA width for Interlaken mode is 64 bits.
For Stratix® V and Arria® V GZ devices, the Interlaken module is an instance of the Interlaken PHY IP core configured for duplex operation, and is generated by the Quartus® Prime parameter editor. The core requires a Stratix® V/ Arria® V GZ Transceiver Reconfiguration Controller for transceiver calibration. The duplex core initially requires as many reconfiguration interfaces as the number of lanes that the IP core uses plus one for the TX PLL. The PMA width is 40 bits.