Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/26/2023

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Document Table of Contents

5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode

For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, this block is an instance of the Native PHY IP core configured for duplex Interlaken operation. The PMA width for Interlaken mode is 64 bits.

For Stratix® V and Arria® V GZ devices, the Interlaken module is an instance of the Interlaken PHY IP core configured for duplex operation, and is generated by the Intel® Quartus® Prime parameter editor. The core requires a Stratix® V/ Arria® V GZ Transceiver Reconfiguration Controller for transceiver calibration. The duplex core initially requires as many reconfiguration interfaces as the number of lanes that the IP core uses plus one for the TX PLL. The PMA width is 40 bits.