Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. Serial Lite III Streaming Intel® FPGA IP Protocol

The Serial Lite III Streaming Intel® FPGA IP implements a protocol that supports high bandwidth data streaming over a unidirectional or bidirectional, high-speed serial link.

The Serial Lite III Streaming Intel® FPGA IP has the following protocol features:

  • Simplex source only, simplex sink only, and duplex (transmitter and receiver) operations
  • Support for single or multiple lanes
  • 64B/67B physical layer encoding
  • Payload and idle scrambling
  • Error detection:
    • Source burst gap mismatch error
    • Error Correction Code (ECC) with 1 bit correction and 2 or more bits detection
    • Sink and source adaptation First In First Out (FIFO) overflow error
    • Sink Cyclic Redundancy Check (CRC) errors
    • Sink Physical Coding Sublayer (PCS) synchronization, metaframe, or CRC errors
  • Low protocol overhead
  • Low point-to-point transfer latency
  • Reduces soft logic resource utilization using hardened Transceiver Native PHY Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA IP and L-Tile/H-Tile/E-Tile Transceiver Intel® Stratix® 10 FPGA IP or Interlaken PHY v18.1 IP ( Stratix® V and Arria® V GZ devices)