Serial Lite III Streaming Intel® FPGA IP User Guide

Download PDF
ID 683330
Date 5/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Intel® Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Intel® Stratix® 10 Devices 3.4.3. Parameter Settings for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Intel® Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Intel® Stratix® 10 Devices 5.9.3. Signals for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Intel® Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Intel® Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

5.8. User Data Interface Waveforms

The following waveforms apply to the Serial Lite III Streaming IP core source user interface in source-only and duplex cores.
Figure 11. Source Waveform for Burst Mode
Figure 12. Source Waveform for Burst Mode (Sync)
Figure 13. Source Waveform for Continuous Mode
  • start_of_burst pulses for one clock cycle, indicating that the data burst starts at that clock cycle.
  • end_of_burst pulses for one clock cycle, indicating that the data burst ends at that clock cycle.
  • The valid signal indicates valid data. It should be turned off between two data bursts that are between the current data burst's end_of_burst clock cycle and next data burst's start_of_burst clock cycle. The valid signal can be pulled low in the middle of a data burst transferring between the same data burst's start_of_burst and end_of_burst, indicating non-valid data at that clock cycle.
  • The sync vector is used in burst mode. It is valid only when start_of_burst and valid are high. Multiple logical channel is time-multiplexed into physical channels. Sync vector can be used to store the logical channel number that the burst targets. The logical channel number is multiplexed into the sync vector during the start_of_burst. The value is embedded into the data and sent over to the receiving party. The sink can extract the channel number from start_of_burst data bus to output on the sync vector of the sink. The sync vector can also be used to include empty information which indicates invalid data at the end_of_burst. In this case, the empty value is multiplexed into the sync vector during end_of_burst. The data is again embedded inside and sent over to the receiving party. The sink extracts the information and output on the sync vector of the sink.

The following waveforms apply to the sink user interface in sink-only and duplex cores.

Figure 14. Sink Waveform for Burst Mode
Figure 15. Sink Waveform for Continuous Mode
  • start_of_burst pulses for one clock cycle, indicating that the data burst starts at that clock cycle.
  • end_of_burst pulses for one clock cycle, indicating that the data burst ends at that clock cycle.
  • The valid signal indicates valid data. It is turned off between two data bursts that are between the current data burst's end_of_burst clock cycle and the next data burst's start_of_burst clock cycle. The valid signal can be pulled low in the middle of a data burst after a data burst's start_of_burst and before the data burst's end_of_burst, indicating non-valid data at that clock cycle.
  • The sync vector is used in burst mode. The sync data picked up at the source's start_of_burst high cycle is sent out at the sink as shown in the waveform. Multiple logical channel is time-multiplexed into physical channels. Sync vector can be used to store the logical channel number that the burst targets. The logical channel number is multiplexed into the sync vector during the start_of_burst. The value is embedded into the data and sent over to the receiving party. The sink can extract the channel number from start_of_burst data bus to output on the sync vector of the sink. The sync vector can also be used to include empty information which indicates invalid data at the end_of_burst. In this case, the empty value is multiplexed into the sync vector during end_of_burst. The data is again embedded inside and sent over to the receiving party. The sink extracts the information and output on the sync vector of the sink.
Level Two Title