Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/26/2023
Public

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8.2.2. Sink Core Link Debugging

Figure 29. Sink Core Link Debugging Flow Chart
Table 52.  Sink Link Debugging Signals ( Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V , and Arria® V GZ devices)

Signal Name

Location

( Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, and Arria® V GZ)

Location

( Intel® Stratix® 10)

Description

rx_aligned

Top level port

Top level port

This active high signal indicates that the lanes are properly aligned. This signal should remain asserted for proper operation.

rx_pcs_ready

Native PHY wrapper port

(Encrypted) Soft PHY port

An asserted value for this active high signal indicates that the reset sequence for the sink PCS is complete.

rx_crc32err

Native PHY wrapper port

PHY top internal

This active high signal indicates CRC-32 error from the CRC checker.

rx_pcs_err _

PHY top port

This active high signal indicates if there is any Sync Header, Meta-frame Length, or CRC32 error. This signal can be used to debug whether there is any data integrity issue on a given meta-frame.

rx_frame_lock [lanes-1:0]

Native PHY wrapper port

PHY top internal

This active high signal indicates that four Interlaken synchronization words are found for a given lane.

rx_block_frame_lock

Native PHY wrapper port

PHY top port

This active high signal indicates whether a link has established both block lock and frame lock link alignment state.

rx_is_lockedtodata [lanes-1:0]

Native PHY wrapper internal

PHY top internal

This active high signal indicates that the transceiver channel PLL has locked itself to the incoming data.

rx_cal_busy

Native PHY wrapper internal

PHY top internal

Sink transceiver calibration status. This active high signal can be used for debugging if the reconfiguration controller is actively calibrating during the initialization sequence.