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1.4.1. Creating the Qsys System
1.4.2. Creating the Transceiver Native PHY IP
1.4.3. Creating the Reconfiguration Controller
1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL
1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL
1.4.6. Creating the Transceiver PHY Reset Controller
1.4.7. Creating a ROM that Contains the MIF for Reconfiguration
1.4.8. Compiling the Design Example
1.4.9. Creating In-System Sources and Probes (ISSP)
1.4.10. Performing Reconfiguration with the System Console Tool
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1.1.1. Register-Based Reconfiguration
Register-based reconfiguration does not require any MIF files during the reconfiguration process. It uses a set of dedicated reconfiguration addresses to carry out a specific reconfiguration function. You use a specific flow to carry out this reconfiguration.
The design example in this application note demonstrates the following:
- The analog (PMA) reconfiguration update on the VOD settings
- The method to trigger the duty cycle distortion (DCD) calibration