Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

ID 683321
Date 12/04/2015
Document Table of Contents

1.4.6. Creating the Transceiver PHY Reset Controller

The design example uses the Transceiver PHY Reset Controller to control the reset sequence of the transceiver channel.

As shown in the figure below, set the Number of TX PLLs field to 2. In this design example, you switch the TX PLL between the CMU PLL and fPLL. Therefore, you must connect both PLL locked signals, pll_locked[1:0], to the reset controller to indicate the release of tx_digitalreset. The reset controller releases tx_digitalreset whenever there is an assertion on either of the pll_locked[1:0] signals. Leave the remaining settings in the PHY Reset Controller to their default values.

Figure 9. Transceiver Reset Controller Parameter Settings

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