Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration

Switch the TX PLL to change the transceiver channel from 2500 Mbps to 5000 Mbps. You can switch the PLL by streaming a MIF.
Table 6.  Steps for Using the Streamer-Based Reconfiguration Mode

Step

Reconfiguration Step

Memory Map Address

Value Written

Description

1

Write to the logical channel register

0x38

0h

Logical channel 0 selected (Physical ch0)

2

Write MIF mode 0 to the control and status register

0x3A

0h

Streamer mode selected

3

Write to the "feature” offset register

0x3B

0h

Select “MIF base address”

4

Write to the data offset register

0x3C

8000h

Specify base address at 8000h 1

5

Write to the “write” bit of the control and status register

0x3A

1h

Trigger "write" operation

6

Write to the "feature” offset register to start the MIF operation

0x3B

1h

Select “Start MIF Stream”

7

Write to the data offset register to trigger the MIF write process

0x3C

1h

Set 1 to trigger the MIF streaming

8

Write to the “write” bit of the control and status register

0x3A

1h

Trigger "write"’ operation

Related Information
1 You can select any base address except the Reconfiguration Controller and Avalon-MM master base address
Level Two Title