Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4. Arria V GX Dynamic Reconfiguration Design Example

The design example uses the Reconfiguration Controller to dynamically reconfigure a Native PHY IP to support multiple data rates of 2500 Mbps and 5000 Mbps by switching the external PLL connected to the transceiver channel. The design example uses a 5AGXFB3H4F35C5 device and is compiled with the Quartus® II 12.1sp1 software.

The reconfiguration commands are controlled through the System Console tool that ships with the Quartus II software. This design example demonstrates the following reconfiguration methods:

  • Streamer-based reconfiguration
    • The MIF streaming reconfiguration is used to switch the TX PLLs that are connected to the transceiver channel.
  • Register-based reconfiguration
    • Changing VOD setting
    • Triggering DCD calibration manually

The design example consists of the following modules. The numbers refer to the position of the modules in the following figure. The system-level diagram shows how the different modules interact in the reconfiguration design example.

  1. Arria V GX Transceiver Native PHY IP
  2. Transceiver Reconfiguration Controller
  3. Qsys system
  4. PHY Reset Controller
  5. CMU PLL – Transceiver PLL
  6. Fractional PLL (fPLL) – Altera fPLL
  7. ROM containing the MIF for reconfiguration
  8. In-System Sources and Probes (ISSP)

The design example also contains a PRBS data generator and checker. The data generator generates a PRBS15 data pattern. The data checker verifies the PRBS15 data received.

Figure 1. System Diagram

System Diagram

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