Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.2. Creating the Transceiver Native PHY IP

The design example uses the Arria V Native PHY IP as a single duplex transceiver channel. Unlike other PHY IP, the Native PHY IP does not include the Avalon-MM interface. Instead, it exposes all signals directly as ports. In this design example, the Native PHY IP interfaces with the Reset Controller, Reconfiguration Controller, and the ISSP.

The Native PHY is created such that two transmit PLLs are used to clock the data channels. Both transmit PLLs are instantiated using external transceiver PLLs. The CMU PLL and fPLL are selected as the external transceiver PLLs. Follow the steps in the following figures to set up the parameters required by the Native PHY to switch between the two external transceiver PLLs.

Figure 3. Datapath Options, TX PMA, and TX PLL0 Settings in Native PHY IP
Figure 4. TX PLL 1 and RX PMA settings in Native PHY IP

Turn on the Enable CDR dynamic reconfiguration option to allow the data rate change of the CDR during streamer-based reconfiguration. With the Reconfiguration Controller connected, you can selectively determine which transmit PLL is used.

Refer to the gxb_duplex.v file in the design example for the standard PCS settings.

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